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Número de pieza

componentes Descripción

Fabricante

NJU6673

25-common x 100-segment BITMAP LCD DRIVER

Japan Radio Corporation  

NJU6673

No.

16

3

15

18

17

8

7

14

Symbol

A0

RES

CS

RD (E)

WR(R/W)

SEL68

P/S

OSC

I/O

Function

I Data discremination signal input terminal. The signal from MPU

discreminates transmitted data between Display data and Instruction.

A0

H

L

Discremination

Display Data

Instruction

I Reset terminal.

Reset operation is executing during “L” state of RES.

I Chip select signal input terminal.

Data Input/Output are available during CS ="L".

I RD(80 type) or E(68 type) signal input terminal.

<In 80 type MPU mode>(SEL68=”L”)

RD signal from 80 type MPU input terminal. Active”L”.

D0 to D7 terminals are output during ”L” level.

<In 68 type MPU mode>(SEL68=”H”)

Enable signal from 68 type MPU input terminal. Active "H"

I WR (80 type) or R/W(68 type) signal input terminal.

<In 80 Type MPU mode>(SEL68=”L”)

WR signal from 80 type MPU input . Active "L".

The data transmitted during WR=”L” are fetched at the rising edge of

WR.

<In 68 Type MPU mode>

R/w signal from 68 type MPU input terminal.

R/W

H

L

State

Read

Write

I MPU interface type selection terminal.

This terminal must connect to VDD or VSS

SEL68

H

L

State

68 type

80 type

I Parallel or Serial interface selection signal input terminal.

P/S

Inter face

Chip Data

Select /Command

Data

Read/Write Serial CLK

“H” Parallel CS

A0

D0-D7 RD, WR

-

“L” Serial CS

A0

SI(D7)

-

SCL(D6)

In case of the serial interface (P/S="L")

RAM data and status read operation do not work in mode of the serial

interface. RD and WR terminals must fix to "H" or "L".

D0 to D5 terminals are high impedance.

O Maker Testing Clock output terminal.

The terminal is recommended to open.

-8-

Ver.2003-04-08

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