NJU6673 Ver la hoja de datos (PDF) - Japan Radio Corporation

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componentes Descripción

Fabricante

NJU6673

25-common x 100-segment BITMAP LCD DRIVER

Japan Radio Corporation  

NJU6673

FUNCTIONAL DESCRIPTION

(1) Description for each blocks

(1-1) Busy Flag (BF)

The Busy Flag (BF) is set to logical “1” in busy of internal execution by an instruction, and any

instruction excepting for the “Status Read” is disable at this time. Busy Flag is outputted through D7

terminal by “Status Read” instruction. Although another instructions should be inputted after check of

Busy Flag, no need to check Busy flag if the system cycle time (tCYC) as shown in s BUS TIMING

CHARACTERISTICS is secured completely.

(1-2) Display Start Line Register

The Display Start Line Register is a register to set a display data RAM address corresponding to the

COM0 display line (the top line normally) for the vertical scroll on the LCD, Page address change and so

forth. The Display Start Line Address set instruction sets the 8-bit display start address into this register.

(1-3) Line Counter

Line Counter is reset when the internal FR signal is switched and outputs the line address of the display

data RAM by count up operation synchronizing with common cycle of NJU6673.

(1-4) Column Address Counter

Column Address Counter is the 8-bit preset-able counter to point the column address of the display data

RAM (DD RAM) as shown in Fig. 1. The counter is incremented automatically after the display data

read/write instructions execution. When the Column address counter reaches to the maximum existing

address by the increment operations, the count up operation (increment) is frozen. However, when new

address is set to the column address counter again, it restarts the count up operation from a set address.

The operation of Column Address Counter is independent against Page Address Register.

By the address inverse instruction (ADC select) as shown in Fig. 1, Column Address Decoder reverses

the correspondence between Column address and Segment output of display data RAM.

(1-5) Page Address Register

Page Address Register assigns the page address of the display data RAM as shown in Fig. 1. In case of

accessing from the MPU with changing the page address, Page Address Set instruction is required.

(1-6) Display Data RAM

The Display data RAM (DD RAM) is the bit map RAM consisting of 2,500 bits to store the display data

corresponding to the LCD pixel on LCD panel.

In Normal Display : “1” Turn-On Display, “0”=Turn-Off Display

In Reveres Display : “1” Turn-Off Display, “0”=Turn-On Display

DD RAM output 100 bits parallel data addressed by line address counter then the data latched in the

display data latch. Asynchronous data access to the DD RAM is available due to the access to the DD

RAM from the MPU and latch to the display data latch operation are done independently.

(1-7) Common Driver Assignment

The scanning order can be assigned by set Common Driver Assignment selection terminal as shown on

Table 1.

Table 1 Common Driver Order Assignment

COM Outputs Terminals

PAD No. 81

95

200

209

Pin name C0

C14

C24

C15

COM Driver Assignment “L”

COM0

COM14

COM24

COM15

selection terminal

“H”

COM24

COM10

COM0

COM9

The duty ratio setting and output assignment register are so controlled to operate independently that

duty ratio setting required to corresponding duty ratio for output assignment.

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Ver.2003-04-08

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