NJ88C30 Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

Número de pieza

componentes Descripción

Fabricante

NJ88C30

VHF SYNTHESISER

Zarlink Semiconductor Inc 

CLOCK

NJ88C30

DATA

DR2

DR1

DR0

DF15

DF1

DF0

DATA SET-UP TIME

DATA

TRANSFER

20

TRANSFER PULSE WIDTH

Fig. 4 Input data timing diagram

180

10

120

0

60

210

0

100k

1M

10M

FREQUENCY (Hz)

100k

1M

10M

FREQUENCY (Hz)

Fig. 5 Gain and phase characteristics of reference oscillator inverter

CIRCUIT DESCRIPTION

Crystal Oscillator and Reference Divider

The Reference oscillator consists of a Pierce type oscillator

intended for use with a parallel resonant fundamental crystal.

Typical gain and phase characteristics for the oscillator inverter

are shown in Fig 5. An external reference oscillator may be

used by either capacitively coupling a 1V RMS sinewave into

CRYSTAL IN (pin 6) or, if CMOS levels are available, by direct

connection to CRYSTAL IN.

The reference oscillator drives a 4100 prescaler followed

by a reference divider to provide a range of comparison

frequencies which are selected by decoding the first three bits

(DR2, DR1, DR0) of the input data. The possible division ratios

and the comparison frequencies (channel spacing) if a 10MHz

crystal is used are shown in Table 1.

DR2 DR1 DR0

Total

division

ratio

Comparison frequency

for 10MHz Ref. Osc.

000

001

010

011

100

101

110

111

1600

800

400

200

2000

1000

500

100

6·25kHz

12·5kHz

25kHz

50kHz

5kHz

10kHz

20kHz

100kHz

Table 1 Reference divider division ratios

To assist in trimming the crystal, an open drain output at one

hundredth of the reference oscillator frequency is provided on

CRYSTAL MONITOR pin 5

Programmable Divider

The programmable divider consists of a 415/16 two modulus

prescaler with a 4-bit control register, followed by a 12-bit

programmable divider. A 1V RMS sinewave should be

capacitively coupled from the VCO to the divider input VCO pin

(pin 10).

The overall division ratio is selected by a single 16-bit word

(DF15 to DF0), loaded through the serial data bus. A lower limit

of 240 ensures correct prescaler operation; the upper limit is

65535. The VCO frequency in a locked system will be this

division ratio multiplied by the comparison frequency.

Phase Comparator

The phase comparator consists of a digital type phase

comparator with open drain f UP and f DN outputs and an

open drain LOCK DETECT (LD) output. Open drain outputs

from the reference divider and programmable divider are

provided for monitoring purposes or for use with an external

phase comparator. Waveforms for all these outputs are shown

in Fig.6. The duty cycle of f UP and f DN versus phase

difference are shown in Fig. 7. The phase comparator is linear

over a ±2π range and if the phase gains or slips by more than

2π, the phase comparator outputs repeat with a 2π period.

3

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