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NE5037

6-Bit A/D converter (parallel outputs)

Philips Electronics 

Philips Semiconductors Linear Products

6-Bit A/D converter (parallel outputs)

Product specification

NE5037

AC ELECTRICAL CHARACTERISTICS

VCC=5.0V; VREF=2.0V; Clock=1MHz; 0°C ≤ TA ≤ 70°C unless otherwise specified. Typical values are specified at 25°C (Refer to AC test

figures.)

SYMBOL

PARAMETER

LIMITS

TO

FROM TEST CONDITIONS

UNIT

Min Typ Max

fMAX

tW

Maximum clock frequency

Start pulse width

Minimum positive/negative

clock pulse width

1

MHz

300

ns

300

ns

tCONV

Conversion time

9 Clock cycles

tP (OUT DATA) Propagation delay1

Data out

OE

TA=25°C tR=tF≤20ns

500

ns

tP (OUT EOC) Propagation delay2

EOC

Clock TA=25°C tR=tF≤20ns

800

ns

tP (3-STATE) Propagation delay, 3-State

3-State Data OE

TA=25°C tR=tF≤20ns

500

ns

NOTES:

1. Propagation delay of data outputs is defined as the delay in the data outputs reading their final value after the low going edge of OE.

2. Propagation delay of EOC is defined as the delay in EOC going low, following the low going edge of the 9th clock pulse after the start pulse.

CIRCUIT DESCRIPTION

The comparator determines whether the output current of the DAC

NE5037 is a complete 6-bit, parallel output, microprocessor

is greater or less than the input current, which is converted from the

compatible, A/D converter which incorporates the

unknown analog input voltage through the V/I converter. If the DAC

successive-approximation method. The chip includes the internal

output is greater, that bit of the DAC is set to ”0’ and the

control logic, the successive-approximation register (SAR), 6-bit

corresponding output buffer goes to ”0’ simultaneously. If it is less, it

DAC, comparator and output buffers. An externally-generated clock

stays at ‘1’ and the output buffer also stays at ‘1’. On successive

source (max frequency=1MHz) must be provided to Pin 6. An

clock pulses, successive bits of the DAC are tried and the

external reference voltage supplied to Pin 2 sets the full-scale range

corresponding output buffer represents the bits of the DAC. On the

of the A/D converter.

eighth low-going edge of the clock pulse (after the receipt of the start

pulse), the EOC pin goes low, thereby indicating that the conversion

The CS pin must be at a low level prior to the start of the conversion

is complete. The output data is now valid. In order to access the

process. Upon receipt of a START pulse, the internal control logic

result of the conversion, the OE pin must be set to a low level. EOC

resets the SAR. On the first low-going edge of the clock pulse,

is reset to a high state when OE is low. When OE is in a ”1’ state,

successive approximation conversion commences. Successive bits

beginning with the MSB (D5) are supplied to the input of the internal

6-bit current output DAC by the I2L successive approximation

ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉ register.

the output buffers are in a high impedance state.

Refer to Figure 1 for the timing diagram.

ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉ CS

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉ DON’TCARE

START

CLK

OE

EOC

DATA

OUTPUTS

HIGH

IMPEDANCE

HIGH

IMPEDANCE

HIGH

IMPEDANCE

DATA

READY

HIGH

AVAILABLE

Figure 1. Timing Diagram

HIGH

AVAILABLE

August 31, 1994

584

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