NCV70501
TYPICAL APPLICATION SCHEMATIC
The application schematic below shows typical
connections for applications with low axis counts and/or
with software SPI implementation. For applications with
many stepper motor drivers, some “minimal wiring”
examples are shown at the last sections of this datasheet.
VDD
R1
R2
100 nF
C2
VBB
D1
C1
22 uF
VBAT
DIR
NXT
DO
MOTXP
DI
NCV 70501
uC
CLK
MOTXN
CSB
M
MOTYP
RHB
ERRB
MOTYN
GND
Figure 4. Typical Application Schematic NCV70501
Table 9. EXTERNAL COMPONENTS LIST AND DESCRIPTION
Component
Function
Typical Value
Tolerance
Unit
C1
VBB buffer capacitor (Note 15)
22
−20 +80%
mF
C2
VBB decoupling capacitor
100
−20 +80%
nF
R1, R2
Pullup resistor
1...5
$10%
kW
D1
Optional reverse protection diode
E.G. SS16
15. Low ESR < 4 W, mounted as close as possible to the NCV70501. The total decoupling capacitance value has to be chosen properly to reduce
the supply voltage ripple and to avoid EM emission.
FUNCTIONAL DESCRIPTION
H−Bridge Drivers with PWM Control
Two H−bridges are integrated to drive a bipolar stepper
motor. Each H−bridge consists of two low−side N−type
MOSFET switches and two high−side P−type MOSFET
switches. One PWM current control loop with on−chip
current sensing is implemented for each H−bridge.
Depending on the desired current range and the micro−step
position at hand, the RDS(on) of the low−side transistors will
be adapted to maintain current−sense accuracy. A
comparator compares continuously the actual winding
current with the requested current and feeds back the
information to generate a PWM signal, which turns on/off
the H−bridge switches. The switching points of the PWM
duty−cycle are synchronized to the on−chip PWM clock. For
each output bridge the PWM duty cycle is measured and
stored in two appropriate status registers of the motor
controller.
The PWM frequency will not vary with changes in the
supply voltage. Also variations in motor−speed or
load−conditions of the motor have no effect. There are no
external components required to adjust the PWM frequency.
In order to avoid large currents through the H−bridge
switches, it is guaranteed that the top− and bottom−switches
of the same half−bridge are never conductive
simultaneously (interlock delay).
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