NCV7361 Ver la hoja de datos (PDF) - ON Semiconductor
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NCV7361 Datasheet PDF : 28 Pages
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NCV7361A
RxD Output
The received BUS signal will be output to the 5.0 V RxD
pin:
BUS < Vthr_cnt – 0.5 * Vthr_hys → RxD = low
BUS > Vthr_cnt + 0.5 * Vthr_hys → RxD = high
This output is a push−pull driver between VOUT and
GND with an output current capability of 1.0 mA.
NCV7361A
VOUT
RxD
MCU
16
14
12
10
8
6
4
2
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VOUT (V)
Figure 22. Output Current of Reset Output vs.
VOUT Voltage
Figure 20. RxD Output Circuitry
Linear Regulator
The NCV7361A has an integrated low dropout linear
regulator with a P−Channel MOSFET output driver whose
output is 5.0 V "2% at v50 mA and 5.5 V v VSUP v
18 V. Figure 21 shows typical current limit based on the
output voltage.
120
100
80
60
40
20
0
0
1
2
3
4
5
6
VOUT (V)
Figure 21. Characteristic of Current Limit
vs. Output Voltage
RESET
RESET switches from low to high if VSUP is switched on
and VOUT > VRES for tRes.
If VOUT drops below VRES, the RESET output goes from
high to low after trr. Short transients will be filtered.
The RESET output driver is driven from VOUT to
guarantee proper operation.
Initialization
The initialization is started if VSUP is switched on. This
is independent of the EN pin.
VSUP Power ON
The NCV7361A starts in the normal mode when VSUP is
applied [>3.15 V (typical)]. The internal circuitry on VOUT
as well as the internal regulator starts the initialization with
power−on−reset. The voltage regulator is switched on.
If VOUT > VPOR the bus−interface will be activated.
If VOUT is higher than VRes, the reset time tRes = 100 ms
is started. After tRes the RESET output switches from low
to high (Figure 22).
The initialization procedure at power on is started
independent from the EN state. The regulator can only be
turned off with a high level followed by a low level on the
EN pin.
Mode Input EN
The NCV7361A is switched into the sleep mode when
EN goes from high to low. The normal mode will be kept
as long as EN = high.
The regulator can be turned off by switching EN high to
low independent of the state of the bus−transceiver.
The EN input is internally pulled down to guarantee a
low with no connection. In the high state, the pulldown
current will be switched off to reduce the quiescent current.
The maximum input voltage is VSUP. The threshold is
typical 2.1 V and therefore CMOS levels can be used as
input signals. Figure 23 shows the internal circuitry of the
EN pin.
The EN input is internally pulled down to secure that if
this pin is not connected a low level will be generated. It
will be used two different pull down current sources for
high and low level to minimize the sleep mode current.
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