MSM5298AGS-BK Ver la hoja de datos (PDF) - Oki Electric Industry

Número de pieza

componentes Descripción

Fabricante

MSM5298AGS-BK

68-DOT COMMON DRIVER

Oki Electric Industry 

¡ Semiconductor

MSM5298A

FUNCTIONAL DESCRIPTION

Pin Functional Description

• IO1, IO68, SHL

IO1 and IO68 are 68-bit bidirectional shift register input/output pins. The shifting direction is

selected by the SHL pin. Refer to the table below.

SHL

Shifting

direction

IO1/IO68

Input/

output

Description

IO1

L

O1 Æ O68

IO68

IO68

H

O68 Æ O1

IO1

Input

Output

Input

Output

The scanning data from the LCD controller LSI is

input into IO1 synchronized with the clock pulse.* 1

Shift register contents output pin. The data which is

input into IO1 is output from IO68 with 68 bit's

delay, synchronized with the clock pulse.

The scanning data from the LCD controller LSI is

input into IO68 synchronized with the clock pulse.* 1

Shift register contents output pin. The data which is

input into IO68 is output from IO1 with 68 bit's delay,

synchronized with the clock pulse.

*1 The combination of the scanning data, IO1 or IO68, and the LCD driving output, O1 to O68,

is shown in the table below.

IO1, IO68

"H"

"L"

LCD driving output

Select level

(V1, VEE)

Non-select level (V2, V5)

• CP

Clock pulse input pin for 68-bit bidirectional shift register. The data is shifted to 68-bit

bidirectional shift register at the falling edge of the clock pulse.

• DF

Alternate signal input pin for LCD driving.

• VDD, VSS

Supply voltage pins. VDD should be 4.5 to 5.5V. VSS is a ground pin. (VSS = 0V).

• DISP OFF

Control input pin for display data output level (O1 to O68). V1 level is output from O1 to O68

pin during "L" level input. Refer to Truth Table.

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