NCP391(2011) Ver la hoja de datos (PDF) - ON Semiconductor

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Fabricante

NCP391
(Rev.:2011)

Positive Overvoltage Protection Controller with Internal Low RON NMOS FET

ON Semiconductor 

NCP391

Undervoltage Lockout (UVLO)

To ensure proper operation under any conditions, the

device has a built−in undervoltage lockout (UVLO) circuit.

During Vin positive going slope, the output remains

disconnected from input until Vin voltage is below UVLO,

plus hysteresis, nominal. The FLAG output is tied to low as

long as Vin does not reach UVLO threshold. This circuit has

a built−in hysteresis to provide noise immunity to transient

condition. Additional UVLO thresholds ranging from

UVLO can be manufactured. Contact your ON

Semiconductor representative for availability.

Overvoltage Lockout (OVLO)

To protect connected systems on Vout pin from

overvoltage, the device has a built−in overvoltage lockout

(OVLO) circuit. During overvoltage condition, the output

remains disabled as long as the input voltage exceeds

typical OVLO. Additional OVLO thresholds ranging from

OVLO can be manufactured. Contact your ON

Semiconductor representative for availability.

FLAG output is tied to low until Vin is higher than OVLO.

This circuit has a built−in hysteresis to provide noise

immunity to transient conditions.

FLAG Output

The NCP391 provides a FLAG output, which alerts

external systems that a fault has occurred.

This pin is tied to low as soon the OVLO threshold is

exceeded or when the Vin level is below the UVLO

threshold. When Vin level recovers normal condition,

FLAG is held high, keeping in mind that an additional tstart

delay has been added between available output and FLAG

= high. The pin is an open drain output, thus a pull up

resistor (typically 1 MW, minimum 10 kW) must be added

to Vbat. Minimum Vbat supply must be 2.5 V. The FLAG

level will always reflects Vin status, even if the device is

turned off (EN = 1).

EN Input

To enable normal operation, the EN pin shall be forced

to low or connected to ground. A high level on the pin,

disconnects OUT pin from IN pin. EN does not overdrive

an OVLO or UVLO fault.

Internal NMOSFET

The NCP391 includes an internal Low RDS(on) NMOS

FET to protect the systems, connected on OUT pin, from

positive overvoltage. Regarding electrical characteristics,

the RDS(on), during normal operation, will create low losses

on Vout pin.

As example: Rload = 8.0 W, Vin = 5.0 V

Typical RDS(on) = 120 mW, Iout = 615 mA

Vout = 8 x 0.615 = 4.926 V

NMOS losses = RDS(on) x Iout2 = 0.12 x 0.6152 = 45 mW

ESD Tests

The NCP391 input pin fully supports the IEC61000−4−2.

1.0 mF (minimum) must be connected between Vin and

GND, close to the device.

That means, in Air condition, Vin has a "15 kV ESD

protected input. In Contact condition, Vin has "8.0 kV

ESD protected input.

Please refer to Figure 19 to see the IEC 61000−4−2

electrostatic discharge waveform.

Figure 19. Electrostatic Discharge Waveform

PCB Recommendations

The NCP391 integrates a 2 A rated NMOSFET, and the

PCB rules must be respected to properly evacuate the heat

out of the silicon.

200

180

160

140

120

100

80

60

0

Theta JA curve with PCB cu thk 1.0 oz

Theta JA curve with PCB cu thk 2.0 oz

Power curve with PCB cu thk 2.0 oz

Power curve with PCB cu thk 1.0 oz

1.75

1.5

1.25

1

0.75

0.5

100 200 300 400 500 600

Copper heat spreader area (mm^2)

Figure 20.

0.25

700

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