OD 3
IN 2
VCC
TSD
UVLO
START STOP
MIN DRVL
OFF TIMER
NCP3488
FALLING
EDGE
DELAY
FALLING
EDGE
DELAY
NON−OVERLAP
TIMERS
MONITOR
MONITOR
Figure 1. Block Diagram
1 BST
8 DRVH
7 SWN
4 VCC
5 DRVL
6 PGND
PIN DESCRIPTION
Pin No. Symbol
Description
1
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this
bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value is between
100 nF and 1.0 mF. An external diode is required with the NCP3488.
2
IN
Logic−Level Input. This pin has primary control of the drive outputs.
3
OD
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
4
VCC
Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.
5
DRVL Output drive for the lower MOSFET.
6
PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7
SWN Switch Node. Connect to the source of the upper MOSFET.
8
DRVH Output drive for the upper MOSFET.
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2