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Fabricante

NCP3020A

Synchronous PWM Controller

ON Semiconductor 

NCP3020A, NCP3020B, NCV3020A, NCV3020B

DETAILED DESCRIPTION

OVERVIEW

The NCP3020A/B operates as a 300/600 kHz, voltage

mode, pulse width modulated, (PWM) synchronous buck

converter. It drives high−side and low−side N−channel power

MOSFETs. The NCP3020 incorporates an internal boost

circuit consisting of a boost clamp and boost diode to provide

supply voltage for the high side MOSFET gate driver. The

NCP3020 also integrates several protection features including

input undervoltage lockout (UVLO), output undervoltage

(OUV), output overvoltage (OOV), adjustable high−side

current limit (ISET and ILIM), and thermal shutdown (TSD).

The operational transconductance amplifier (OTA)

provides a high gain error signal from Vout which is

compared to the internal 1.5 V pk-pk ramp signal to set the

duty cycle converter using the PWM comparator. The high

side switch is turned on by the positive edge of the clock

cycle going into the PWM comparator and flip flop

following a non-overlap time. The high side switch is turned

off when the PWM comparator output is tripped by the

modulator ramp signal reaching a threshold level

established by the error amplifier. The gate driver stage

incorporates fixed non− overlap time between the high−side

and low−side MOSFET gate drives to prevent cross

conduction of the power MOSFET’s.

POR and UVLO

The device contains an internal Power On Reset (POR) and

input Undervoltage Lockout (UVLO) that inhibits the internal

logic and the output stage from operating until VCC reaches its

respective predefined voltage levels (4.3 V typical).

Startup and Shutdown

Once VCC crosses the UVLO rising threshold the device

begins its startup process. Closed−loop soft−start begins

after a 400 ms delay wherein the boost capacitor is charged,

and the current limit threshold is set. During the 400 ms delay

the OTA output is set to just below the valley voltage of the

internal ramp. This is done to reduce delays and to ensure a

consistent pre−soft−start condition. The device increases the

internal reference from 0 V to 0.6 V in 24 discrete steps

while maintaining closed loop regulation at each step. Each

step contains 64 switching cycles. Some overshoot may be

evident at the start of each step depending on the voltage

loop phase margin and bandwidth. The total soft−start time

is 6.8 ms for the NCP3020A and 4.4 ms for the NCP3020B.

25 mV Steps

0.6 V

24 Voltage Steps

Internal Reference Voltage

Internal Ramp

OTA Output

0.7 V

0V

Figure 21. Soft−Start Details

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