NCP3020A Ver la hoja de datos (PDF) - ON Semiconductor

Número de pieza

componentes Descripción

Fabricante

NCP3020A

Synchronous PWM Controller

ON Semiconductor 

NCP3020A, NCP3020B, NCV3020A, NCV3020B

OOV and OUV

The output voltage of the buck converter is monitored at

the feedback pin of the output power stage. Two

comparators are placed on the feedback node of the OTA to

monitor the operating window of the feedback voltage as

shown in Figures 22 and 23. All comparator outputs are

ignored during the soft−start sequence as soft−start is

regulated by the OTA and false trips would be generated.

After the soft−start period has ended, if the feedback is

below the reference voltage of comparator 2 (VFB < 0.45 V),

the output is considered “undervoltage” and the device will

initiate a restart. When the feedback pin voltage rises

between the reference voltages of comparator 1 and

comparator 2 (0.45 < VFB < 0.75), then the output voltage

is considered “Power Good.” Finally, if the feedback voltage

is greater than comparator 1 (VFB > 0.75 V), the output

voltage is considered “overvoltage,” and the device will

latch off. To clear a latch fault, input voltage must be

recycled. Graphical representation of the OOV and OUV is

shown in Figures 24 and 25.

Vref*125%

Soft Start Complete

Comparator 1

Restart

FB

Vref = 0.6 V

LOGIC

Vref*75%

Comparator 2

Figure 22. OOV and OUV Circuit Diagram

Latch off

Hysteresis = 5 mV

Hysteresis = 5 mV

OOVP & Power Good = 0

Power Good = 1

Power Good = 1

OUVP & Power Good = 0

Voov = Vref * 125%

Power Not good High

Vref = 0.6 V

Power Not Good Low

Vouv = Vref * 75%

Figure 23. OOV and OUV Window Diagram

http://onsemi.com

10

Share Link: