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componentes Descripción

Fabricante

NCP3012

Synchronous PWM Controller

ON Semiconductor 

NCP3012

where:

tON

+

QGD

IG1

+

ǒVBST

*

QGD

VTHǓńǒRHSPU

)

RGǓ

(eq. 32)

and:

tOFF

+

QGD

IG2

+

ǒVBST

*

QGD

VTHǓńǒRHSPD

)

RGǓ

(eq. 33)

Next, the MOSFET output capacitance losses are caused

by both the control and synchronous MOSFET but are

dissipated only in the control MOSFET.

PDS

+

1

2

@

QOSS

@

VIN

@

fSW

(eq. 34)

Finally the loss due to the reverse recovery time of the

body diode in the synchronous MOSFET is shown as

follows:

PRR + QRR @ VIN @ fSW

(eq. 35)

The low−side or synchronous MOSFET turns on into zero

volts so switching losses are negligible. Its power

dissipation only consists of conduction loss due to RDS(on)

and body diode loss during the non−overlap periods.

PD_SYNC + PCOND ) PBODY

(eq. 36)

Conduction loss in the low−side or synchronous

MOSFET is described as follows:

ǒ Ǔ2

PCOND + IRMS_SYNC @ RDS(on)_SYNC (eq. 37)

where:

Ǹ ǒ ǒ ǓǓ IRMS_SYNC + IOUT @

(1 * D) @ 1 ) ra2

12

(eq. 38)

The body diode losses can be approximated as:

PBODY + VFD @ IOUT @ fSW @ ǒNOLLH ) NOLHLǓ (eq. 39)

Vth

IG1: output current from the high−side gate drive (HSDR)

IG2: output current from the low−side gate drive (LSDR)

ƒSW: switching frequency of the converter.

VBST: gate drive voltage for the high−side drive, typically

7.5 V.

QGD: gate charge plateau region, commonly specified in the

MOSFET datasheet

VTH: gate−to−source voltage at the gate charge plateau

region

QOSS: MOSFET output gate charge specified in the data

sheet

QRR: reverse recovery charge of the low−side or

synchronous MOSFET, specified in the datasheet

RDS(on)_CONTROL: on resistance of the high−side, or

control, MOSFET

RDS(on)_SYNC: on resistance of the low−side, or

synchronous, MOSFET

NOLLH: dead time between the LSDR turning off and the

HSDR turning on, typically 85 ns

NOLHL: dead time between the HSDR turning off and the

LSDR turning on, typically 75 ns

Once the MOSFET power dissipations are determined,

the designer can calculate the required thermal impedance

for each device to maintain a specified junction temperature

at the worst case ambient temperature. The formula for

calculating the junction temperature with the package in free

air is:

TJ + TA ) PD @ RqJA

TJ: Junction Temperature

TA: Ambient Temperature

PD: Power Dissipation of the MOSFET under analysis

RqJA: Thermal Resistance Junction−to−Ambient of the

MOSFET’s package

As with any power design, proper laboratory testing

should be performed to insure the design will dissipate the

required power under worst case operating conditions.

Variables considered during testing should include

maximum ambient temperature, minimum airflow,

maximum input voltage, maximum loading, and component

variations (i.e. worst case MOSFET RDS(on)).

Figure 34. MOSFET Switching Characteristics

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