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componentes Descripción

Fabricante

NCP3012

Synchronous PWM Controller

ON Semiconductor 

NCP3012

Output Capacitor Selection

The important factors to consider when selecting an

output capacitor is dc voltage rating, ripple current rating,

output ripple voltage requirements, and transient response

requirements.

The output capacitor must be rated to handle the ripple

current at full load with proper derating. The RMS ratings

given in datasheets are generally for lower switching

frequency than used in switch mode power supplies but a

multiplier is usually given for higher frequency operation.

The RMS current for the output capacitor can be calculated

below:

CoRMS

+

IO

@

ra

Ǹ12

(eq. 20)

The maximum allowable output voltage ripple is a

combination of the ripple current selected, the output

capacitance selected, the equivalent series inductance (ESL)

and ESR.

The main component of the ripple voltage is usually due

to the ESR of the output capacitor and the capacitance

selected.

ǒ Ǔ VESR_C + IO @ ra @

ESRCo

)

8

@

1

FSW

@

Co

(eq. 21)

The ESL of capacitors depends on the technology chosen

but tends to range from 1 nH to 20 nH where ceramic

capacitors have the lowest inductance and electrolytic

capacitors then to have the highest. The calculated

contributing voltage ripple from ESL is shown for the switch

on and switch off below:

VESLON

+

ESL

@

IPP

D

@

FSW

(eq. 22)

VESLOFF

+

ESL @

(1

IPP @ FSW

* D)

(eq. 23)

The output capacitor is a basic component for the fast

response of the power supply. In fact, during load transient,

for the first few microseconds it supplies the current to the

load. The controller immediately recognizes the load

transient and sets the duty cycle to maximum, but the current

slope is limited by the inductor value.

During a load step transient the output voltage initially

drops due to the current variation inside the capacitor and the

ESR (neglecting the effect of the effective series inductance

(ESL)).

DVOUT−ESR + DITRAN @ ESRCo

(eq. 24)

A minimum capacitor value is required to sustain the

current during the load transient without discharging it. The

voltage drop due to output capacitor discharge is

approximated by the following equation:

ǒ Ǔ DVOUT−DISCHG +

ǒITRANǓ2 @ LOUT

COUT @ VIN * VOUT

(eq. 25)

In a typical converter design, the ESR of the output capacitor

bank dominates the transient response. It should be noted

that DVOUT−DISCHARGE and DVOUT−ESR are out of

phase with each other, and the larger of these two voltages

will determine the maximum deviation of the output voltage

(neglecting the effect of the ESL).

Conversely during a load release, the output voltage can

increase as the energy stored in the inductor dumps into the

output capacitor. The ESR contribution from Equation 21

still applies in addition to the output capacitor charge which

is approximated by the following equation:

DVOUT−CHG

+

ǒITRANǓ2 @ LOUT

COUT @ VOUT

(eq. 26)

Power MOSFET Selection

Power dissipation, package size, and the thermal

environment drive MOSFET selection. To adequately select

the correct MOSFETs, the design must first predict its power

dissipation. Once the dissipation is known, the thermal

impedance can be calculated to prevent the specified

maximum junction temperatures from being exceeded at the

highest ambient temperature.

Power dissipation has two primary contributors:

conduction losses and switching losses. The control or

high−side MOSFET will display both switching and

conduction losses. The synchronous or low−side MOSFET

will exhibit only conduction losses because it switches into

nearly zero voltage. However, the body diode in the

synchronous MOSFET will suffer diode losses during the

non−overlap time of the gate drivers.

Starting with the high−side or control MOSFET, the

power dissipation can be approximated from:

PD_CONTROL + PCOND ) PSW_TOT (eq. 27)

The first term is the conduction loss of the high−side

MOSFET while it is on.

ǒ Ǔ2

PCOND + IRMS_CONTROL @ RDS(on)_CONTROL (eq. 28)

Using the ra term from Equation 9, IRMS becomes:

Ǹ ǒ ǒ ǓǓ IRMS_CONTROL + IOUT @

D @ 1 ) ra2

12

(eq. 29)

The second term from Equation 27 is the total switching

loss and can be approximated from the following equations.

PSW_TOT + PSW ) PDS ) PRR

(eq. 30)

The first term for total switching losses from Equation 30

includes the losses associated with turning the control

MOSFET on and off and the corresponding overlap in drain

voltage and current.

PSW + PTON ) PTOFF

+

1

2

@

ǒIOUT

@

VIN

@

fSWǓ

@

ǒtON

)

tOFFǓ

(eq. 31)

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