NB3N5573 Ver la hoja de datos (PDF) - ON Semiconductor

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componentes Descripción

Fabricante

NB3N5573

3.3V, Crystal - To- HCSL Clock Generator

ON Semiconductor 

NB3N5573

S0

1

S1

2

NC

3

16

VDD

15

CLK0

14

CLK0

X1/CLK

4

X2

5

OE

6

GND

7

NC

8

13

GND

12

VDD

11

CLK1

10

CLK1

9

IREF

Figure 2. Pin Configuration (Top View)

Table 1. PIN DESCRIPTION

Pin

Symbol

I/O

Description

1

S0

Input

LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDD. See output

select table 2 for details.

2

S1

Input

LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDD. See output

select Table 2 for details.

12, 16

4

VDD

X1/CLK

Power Supply

Input

Positive supply voltage pins are connected to +3.3 V supply voltage.

Crystal or Clock input. Connect to 25 MHz crystal source or single-ended clock.

5

X2

Input

Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input.

6

7, 13

OE

GND

Input

Power Supply

Output enable tri-states output when connected to GND. Internal pullup resistor to VDD.

Ground 0 V. These pins provide GND return path for the devices.

9

IREF

Output

Output current reference pin. Precision resistor (typ. 475 W) is connected to set the

output current.

11

CLK1

HCSL Output Noninverted clock output.

10

CLK1

HCSL Output Inverted clock output.

15

CLK0

HCSL Output Noninverted clock output.

14

CLK0

HCSL Output Inverted clock output.

3, 8

NC

Do not connect

Table 2. OUTPUT FREQUENCY SELECT TABLE

S1

S0

L

L

fCLKout (MHz)

25

L

H

100

H

L

125

H

H

200

Recommended Crystal Parameters

Crystal

Frequency

Load Capacitance

Shunt Capacitance, C0

Equivalent Series Resistance

Initial Accuracy at 25 °C

Temperature Stability

Aging

C0/C1 Ration

Fundamental AT-Cut

25 MHz

16-20 pF

7 pF Max

35 W Max

±20 ppm

±30 ppm

±20 ppm

250 Max

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