NB6L14S(2009) Ver la hoja de datos (PDF) - ON Semiconductor
Número de pieza
componentes Descripción
Fabricante
NB6L14S
(Rev.:2009)
(Rev.:2009)
ON Semiconductor
NB6L14S Datasheet PDF : 11 Pages
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NB6L14S
Q0 Q0 VCC GND
16 15 14 13
Exposed Pad (EP)
Q1 1
Q1 2
Q2 3
Q2 4
NB6L14S
12 IN
11 VT
10 VREFAC
9 IN
5 678
Q3 Q3 VCC EN
Figure 3. NB6L14S Pinout, 16−pin QFN (Top View)
Table 1. TRUTH TABLE
IN
IN
EN
Q
0
1
1
0
1
0
1
1
x
x
0
0 (Note 1)
1. On next transition of the input signal (IN).
Q
1
0
1 (Note 1)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
Q1
LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2
Q1
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
3
Q2
LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4
Q2
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5
Q3
LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
6
Q3
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
7
VCC
−
Positive Supply Voltage.
8
EN
LVTTL / LVCMOS Input Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb
outputs will go HIGH on the next negative transition of IN input. The internal
DFF register is clocked on the falling edge of IN input; see Figure 26. The EN
pin has an internal pullup resistor and defaults HIGH when left open.
9
IN
LVPECL, CML, LVDS
Inverted Differential Input
10
VREFAC
LVPECL Output
The VREFAC reference output can only be used to rebias capacitor−coupled
differential or single−ended input signals. For the capacitor−coupled IN and/or
INb inputs, VREFAC should be connected to the VT pin and bypassed to ground
with a 0.01 mF capacitor.
11
VT
LVPECL Output
Internal 100 W Center−tapped Termination Pin for IN and IN
12
IN
LVPECL, CML, LVDS
Non−inverted Differential Input. (Note 2)
13
GND
−
Negative Supply Voltage.
14
VCC
15
Q0
−
LVDS Output
Positive Supply Voltage.
Non−inverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
16
Q0
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
−
EP
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is not electrically connected to the
die, but is recommended to be electrically and thermally connected to GND on
the PC board.
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied
on IN/IN inputs, then the device will be susceptible to self−oscillation.
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