NB2304AI1DR2G Ver la hoja de datos (PDF) - ON Semiconductor

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NB2304AI1DR2G

3.3 V Zero Delay Clock Buffer

ON Semiconductor 

NB2304A

Zero Delay and Skew Control

For applications requiring zero input−output delay, all

outputs must be equally loaded.

1500

1000

500

0

−500

To close the feedback loop of the NB2304A, the FBK pin

can be driven from any of the four available output pins. The

output driving the FBK pin will be driving a total load of

7 pF plus any additional load that it drives. The relative

loading of this output (with respect to the remaining outputs)

can adjust the input output delay. This is shown in Figure 3.

For applications requiring zero input−output delay, all

outputs including the one providing feedback should be

equally loaded. If input−output delay adjustments are

required, use Figure 3 to calculate loading differences

between the feedback output and remaining outputs. For

zero output−output skew, be sure to load outputs equally.

−1000

−1500

−30 −25 −20 −15 −10 −5 0 5 10 15 20 25 30

OUTPUT LOAD DIFFERENCE: FBK LOAD − CLKA/CLKB LOAD (pF)

Figure 3. REF Input to CLKA/CLKB Delay vs.

Difference in Loading between FBK Pin and

CLKA/CLKB Pins

SWITCHING WAVEFORMS

1.4 V

t1

t2

1.4 V

1.4 V

Figure 4. Duty Cycle Timing

OUTPUT

2.0 V

0.8 V

t3

2.0 V

0.8 V

t4

3.3 V

0V

Figure 5. All Outputs Rise/Fall Time

OUTPUT

1.4 V

OUTPUT

t5

1.4 V

Figure 6. Output − Output Skew

VDD

2

INPUT

VDD

OUTPUT

2

t6

Figure 7. Input − Output Propagation Delay

FBK_Device 1

FBK_Device 2

VDD

2

t7

VDD

2

Figure 8. Device − Device Skew

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