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HYS72V16220GU

3.3 V 8M × 64/72-Bit 1 Bank SDRAM Module, 3.3 V 16M × 64/72-Bit 2 Bank SDRAM Module

Infineon Technologies 

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

AC Characteristics 3, 4

TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns

Parameter

Symbol

Limit Values

Unit

-8

-8B

PC100-222 PC100-323

-10

PC66

min. max. min. max. min. max.

Note

Clock and Clock Enable

Clock Cycle Time

tCK

CAS Latency = 3

CAS Latency = 2

System Frequency

fCK

CAS Latency = 3

CAS Latency = 2

Clock Access Time

tAC

CAS Latency = 3

CAS Latency = 2

Clock High Pulse Width

Clock Low Pulse Width

Input Setup Time

Input Hold Time

CKE Setup Time

(Power down mode)

tCH

tCL

tCS

tCH

tCKSP

CKE Setup Time

(Self Refresh Exit)

tCKSR

Transition Time

tT

(rise and fall)

10 –

10 –

10 –

ns

10 –

12 –

15 –

ns

–

100 –

100 –

100 MHz

–

100 –

83 –

66 MHz

–

6

–

6

3

–

3

–

2

–

1

–

2.5 –

8

–

–

6

–

7

3

–

3

–

2

–

1

–

2.5 –

10 –

–

8

–

9

3.5 –

3.5 –

3

–

1

–

3

–

8

–

ns

4, 5

ns

ns

6

ns

6

ns

7

ns

7

ns

8

ns

9

1

–

1

–

1

–

ns

Common Parameters

RAS to CAS delay

tRCD

Precharge Time

tRP

Active Command Period

tRAS

Cycle Time

tRC

Bank to Bank Delay Time tRRD

CAS to CAS Delay Time

tCCD

(same bank)

20 –

20 –

30 –

ns

20 –

30 –

30 –

ns

50 100k 60 100k 70 100k ns

70 –

80 –

80 –

ns

16 –

20 –

20 –

ns

1

–

1

–

1

–

CLK

Semiconductor Group

9

1998-08-01

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