MX25L1635DM2I Ver la hoja de datos (PDF) - Macronix International
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MX25L1635DM2I Datasheet PDF : 50 Pages
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MX25L1635D
GENERAL DESCRIPTION
The MX25L1635D are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When it is in
two or four I/O read mode, the structure becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. The MX25L1635D feature a
serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock
input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2
pin and SIO3 pin for address/dummy bits input and data output.
The MX25L1635D provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified
page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis,
or word basis for Continuously program mode, and erase command is executes on sector (4K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for more
details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA(typical:1uA) DC
current.
The MX25L1635D utilizes MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000
program and erase cycles.
Table 1. Additional Feature Comparison
Additional
Featu-
res
Part Name
Protection and Security
Flexible
Block
protection
(BP0-BP3)
512-bit
secured OTP
Read
Performance
Identifier
2 I/O
Read
(75MHz)
4 I/O
RES
REMS
REMS2
REMS4
Read (command : (command : (command : (command :
(75MHz) AB hex)
90 hex)
EF hex)
DF hex)
RDID
(command:
9F hex)
MX25L1635D
V
C2 24 (hex) C2 24 (hex) C2 24 (hex)
V
V
V
24 (hex) (if ADD=0) (if ADD=0) (if ADD=0) C2 24 15 (hex)
MX25L1605D
V
V
V
C2 14 (hex) C2 14 (hex)
14 (hex) (if ADD=0) (if ADD=0)
X
C2 20 15 (hex)
P/N: PM1374
REV. 1.5, OCT. 01, 2008
7
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