MX23L6454 Ver la hoja de datos (PDF) - Macronix International

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Fabricante

MX23L6454

64M-BIT Low Voltage, Serial Mask ROM Memory with 50MHz SPI Bus Interface

Macronix International 

MX23L6454

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must not be

selected (that is Chip Select (S#) must follow the voltage

applied on VCC ) until VCC reaches the correct value:

- VCC(min) at Power-up, and then for a further delay of

tVSL

- VSS at Power-down

Usually a simple pull-up resistor on Chip Select (S#) can

be used to insure safe and proper Power-up and Power-

down.

To avoid data corruption and inadvertent write operations

during power up, a Power On Reset (POR) circuit is

included. The logic inside the device is held reset while

VCC is less than the POR threshold value, VWI -- all

operations are disabled, and the device does not respond

to any instruction.

These values are specified in Table 2.

If the delay, tVSL, has elapsed, after VCC has risen

above VCC (min), the device can be selected for READ

instructions even if the tPUW delay is not yet fully

elapsed.

At Power-up, the device is in the following state:

- The device is in the Standby mode.

Normal precautions must be taken for supply rail

decoupling, to stablise the VCC feed. Each device in a

system should have the VCC rail decoupled by a suitable

capacitor close to the package pins.

(Generally, this capacitor is of the order of 0.1uF).

At Power-down, when VCC drops from the operating

voltage, to below the POR threshold value, VWI , all

operations are disabled and the device does not respond

to any instruction.

Figure 6. Power-up Timing

VCC

VCC(max)

Chip Selection Not Allowed

VCC(min)

Reset State

of the

Device

VWI

tVSL

tPUW

Read Access allowed

Device fully

accessible

time

P/N: PM1127

REV. 1.1, MAR. 09, 2005

9

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