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MV8870 Datasheet PDF : 13 Pages
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MV8870/MV8870-1
DIFFERENTIAL INPUT CONFIGURATION
The input arrangement of the MV8870 / MV8870-1
provides a differential input op. amp. and a bias source (VREF)
to bias the inputs at mid-rail. The gain may be adjusted through
a feedback resistor from the op. amp. output (GS). In a single-
ended configuration the input pins are connected as shown in
Fig. 7 where the op. amp. is connected to give unity gain and
the VREF pin biases the input at (VDD ÷ 2).
Fig.9 shows the differential configuration. In this circuit gain
is adjusted through the feedback resistor R5.
CRYSTAL OSCILLATOR
The internal clock circuit is completed with the addition of
an external 3.58MHz crystal which is normally connected as
shown in Fig. 7. However it is possible to configure several
MV8870 / MV8870-1 devices to use only a single oscillator
crystal.
The devices are chained together with the oscillator output
of the first device in the chain capacitively coupled to the
oscillator input of the second device and so on down the chain.
The details are shown in Fig. 10. Precision balancing
capacitors are not required as problems of unbalanced loading
are not a concern.
RECEIVER SYSTEM FOR BT SPECIFICATION POR 1151
The circuit shown in Fig.11 illustrates the use of the
MV8870-1 in a typical receiver system. The BT specification
defines the non-operate level as input signals below 34 dBm.
This is obtained by choosing R1 and R2 to give 3dB of
attenuation so that an input of 34 dBm corresponds to -37 dBm
at the op. amp. output pin (GS). The tolerances on R3 and C2
give a tolerance on guard time of 6%. For better performance
the non-symmetric guard time circuit shown in Fig.12 is
recommended.
C1
C2
R1
R4
1 IN+ +
2 IN- -
R5 3 GS
R3
R2
4 VREF
MV8870/
MV8870-1
Differential Input Amplifier
C1 = C2 = 0.01µF
R1 = R4 = R5 = 100kΩ
Resistors are ± 1%
R2 = 60kΩ
Capacitors are ± 5%
R3 = R2R5 ÷ (R2 + R5)
Voltage Gain (AVdiff) = R5 ÷ R1
Input Impedance
ZINDIFF = 2[R12 + (1 ÷ wC)2]1/2
Figure 9: Differential input configuration
MV8870/
MV8870-1
OSC1 7 X
OSC2 8
MV8870/
MV8870-1
C
7 OSC1
C
8 OSC2
C = 30pF
X = 3.57945MHz
To OSC1
of next
MV8870/
MV8870-1
Figure 10: Oscillator circuit
DTMF
INPUT
C1
R1
R2
X
MV8870/
MV8870-1
1
IN+
18
VDD
2
IN-
17
St/GT
3
GS
16
ESt
4
VREF
15
StD
5
SEL
14
Q4
6
PD
13
Q3
7
OSC1
12
Q2
8 OSC2
11
Q1
9 VSS
10
TOE
VDD
C2
R3
} DECODED
OUTPUT
R1 = 102kΩ ± 1%
R2 = 71.5kΩ ± 1%
R3 = 390kΩ ± 1%
C1, C2 = 0.1µF ± 5%
X = 3.579545MHz ± 0.1%
Figure 11: Single ended circuit for BT/CEPT Specs
18
VDD
MV8870/
17
St/GT
MV8870-1
16
ESt
15
StD
VDD
C
R1
R2
tGTA = R1C In {VDD ÷ VTSt}
tGTP = RPC In {VDD ÷ [VDD - VTSt]}
RP = R1R2 ÷ {R1 + R2}
R1 = 368kΩ ± 1%
R2 = 2.2mΩ ± 1%
C = 0.1µF ± 5%
Figure 12: Non-symmetric guard time circuit
5
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