VITESSE
SEMICONDUCTOR CORPORATION
64x64 Crosspoint Switch
Advance Product Information
VSC6464
Application Notes
Figure 8 Multiple-Crosspoint Synchronous System Configuration
SYSTEM_CK
DATA_IN
REG
XPNT0
DIN
DOUT
REG
DATA_OUT
XPNT_0_SEL
SERIAL_CK
MODE = ‘1’
SERIAL_DATA
XPNT_1_SEL
DATA_IN
REG
XPNT1
DIN
DOUT
REG
DATA_OUT
SYSTEM_CK
High-speed designs using single-ended ECL signals need careful design to avoid noise and crosstalk prob-
lems. The following suggestions can aid obtaining a reliable system:
1. Wide noise margins on input signals.
2. Avoid SSOs. Simultaneous switching outputs will degrade timing margins by increasing AC delay val-
ues, and reducing noisethresholds.
3. Provide good signal terminations and well-matched board traces in addition to well-controlled power
supplies.
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© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52219-0, Rev. 2.0
8/4/98