MSM5718C50-53GS-K Ver la hoja de datos (PDF) - Oki Electric Industry

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MSM5718C50-53GS-K

18Mb (2M x 9) & 64Mb (8M x 8) Concurrent RDRAM

Oki Electric Industry 

¡ Semiconductor

MSM5718C50/MD5764802

GENERAL DESCRIPTION

Figure 3 is a block diagram of an RDRAM. At the bottom is a standard DRAM core organized as two

or four independent banks, with each bank organized as 512 or 1024 rows, and with each row

consisting of 2KBytes of memory cells. One row of a bank may be “activated” at any time (ACTV

command) and placed in the 2KByte “page” for the bank. Column accesses (READ and WRITE

commands) may be made to this active page.

The smallest block of memory that may be accessed with READ and WRITE commands is an octbyte

(eight bytes). Bitmask and bytemask options are available with the WRITE command to allow finer

write granularity. There are six control registers that are accessed at initialization time to configure

the RDRAM for a particular application.

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