¡ Semiconductor
MSM5718C50/MD5764802
Table 2 Pin Descriptions
Signal
DQ8..DQ0
(BUSDATA [8:0])
CLK
(RXCLK)
CLK
(TXCLK)
VREF
COMMAND
(BUSCTRL)
ADDRESS
(BUSENABLE)
VDD, VDDA
GND, GNDA
SIN
SOUT
I/O
Description
Signal lines for REQ, DIN, and DOUT packets. The REQ packet contains the
I/O
address field, command field, and other control fields. These are RSL
signals.a
I
Receive clock. All input packets are aligned to this clock. This is an RSL
signal.a
I
Transmit clock. DOUT packets are aligned with this clock. This is an RSL
signal.a
I
Logic threshold reference voltage for RSL signals.
I
Signal line for REQ, RSTRB, RTERM, WSTRB, WTERM, RESET, and CKE
packets. This is an RSL signal.a
I
Signal line for COL packets with column addresses. This is an RSL signal.a
—
+3.3 V power supply. VDDA is a separate analog supply for clock generation
in the RDRAM.
—
Circuit ground. GNDA is a separate analog ground for clock generation in
the RDRAM.
I
Initialization daisy chain input. CMOS levels.
O
Initialization daisy chain output. CMOS levels.
a. RSL stands for Rambus Signaling Levels, a low-voltage-swing, active-low signaling technology.
Mechanical
Support Pins
Pin 1
Pin 32
Mechanical
Support Pins
Fig. 2 SHP Package
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