CY7C0430V-100BGC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C0430V-100BGC Datasheet PDF : 36 Pages
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PRELIMINARY
Pin Definitions (continued)
Port 1
CNTRDP1
Port 2
CNTRDP2
Port 3
CNTRDP3
Port 4
CNTRDP4
MKRDP1
MKRDP2
MKRDP3
MKRDP4
CNTINTP1
INTP1
CNTINTP2
INTP2
CNTINTP3
INTP3
CNTINTP4
INTP4
TMS
TCK
TDI
TDO
CLKBIST
GND
VSS
VDD
VSS1
VDD1
VSS2
VDD2
CY7C0430V
Description
Counter Readback Input. When asserted LOW, the inter-
nal address value of the counter will be read back on the
address lines. During CNTRD operation, both CNTLD
and CNTINC must be HIGH. Counter readback operation
has higher priority over mask register readback opera-
tion. Counter readback operation is independent of port
chip enables. If address readback operation occurs with
chip enables active (CE0 = LOW, CE1 = HIGH), the data
lines (I/Os) will be three-stated. The readback timing will
be valid after one no-operation cycle plus tCD2 from the
rising edge of the next cycle.
Mask Register Readback Input. When asserted LOW, the
value of the mask register will be readback on address
lines. During mask register readback operation, all
counter and MKLD inputs must be HIGH (see Counter
and Mask Register Operations truth table). Mask register
readback operation is independent of port chip enables.
If address readback operation occurs with chip enables
active (CE0 = LOW, CE1 = HIGH), the data lines (I/Os)
will be three-stated. The readback will be valid after one
no-operation cycle plus tCD2 from the rising edge of the
next cycle.
Counter Interrupt flag output. Flag is asserted LOW for
one clock cycle when the counter wraps around to loca-
tion zero.
Interrupt flag output. Interrupt permits communications
between all four ports. The upper four memory locations
can be used for message passing. Example of operation:
INTP4 is asserted LOW when another port writes to the
mailbox location of Port 4. Flag is cleared when Port 4
reads the contents of its mailbox. The same operation is
applicable to Ports 1, 2, and 3.
JTAG Test Mode Select Input. It controls the advance of
JTAG TAP state machine. State machine transitions oc-
cur on the rising edge of TCK.
JTAG Test Clock Input. This can be CLK of any port or an
external clock connected to the JTAG TAP.
JTAG Test Data Input. This is the only data input. TDI
inputs will shift data serially in to the selected register.
JTAG Test Data Output. This is the only data output. TDO
transitions occur on the falling edge of TCK. TDO normal-
ly three-stated except when captured data is shifted out
of the JTAG TAP.
BIST Clock Input.
Thermal ground for heat dissipation.
Ground Input.
Power Input.
Address lines ground Input.
Address lines power Input.
Data lines ground Input.
Data lines power Input.
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