PIN DESCRIPTIONS
Pin Locations
30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50,
81, 83, 85, 98, 100
3, 5, 9, 11, 16, 18, 22, 24, 28, 52, 56, 58,
62, 64, 69, 71, 75, 77
90
91
92
96
86
4, 6, 10, 12, 15, 17, 21, 23, 27, 53, 57,
59, 63, 65, 68, 70, 74, 76
88
1, 7, 13, 19, 25, 41, 54, 60, 66, 72, 78, 95
2, 8, 14, 20, 26, 55, 61, 67, 73, 79, 94
29, 31, 33, 35, 37, 39, 43, 45, 47, 49, 51,
80, 82, 84, 87, 89, 93, 97, 99
Symbol
A0 – A15
D0 – D17
E1
E2
G
K
PT
Q0 – Q17
W
VDD
VSS
NC
Type
Input
Input
Description
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Data Input.
Input Synchronous Chip Enable: Active low for depth expansion.
Input Synchronous Chip Enable: Active high for depth expansion.
Input
Asynchronous Output Enable Input:
Low — enables output buffers (Qx pins).
High — Qx pins are high impedance.
Input Clock: This signal registers the address, data in, and all control signals
except G.
Input Pass–through enable: Synchronous.
Output Synchronous Data Output.
Input Synchronous Write.
Supply + 3.3 V Power Supply.
Supply Ground.
— No Connection: There is no connection to the chip.
TRUTH TABLE
Operation
Input at tn Clock
E1
E2
W
PT
Data Input D
Write and Pass–Through L
H
L
L
D written to A
Write/Read
L
H
L
H
D written to A
Pass–Through
L
H
H
L
D data
Read
L
H
H
H
Don’t Care
Deselected
X
L
X
X
Don’t Care
Deselected
H
X
X
X
Don’t Care
NOTES:
1. Write D to array and output D at Q.
2. Output contents of array to Q then write D to array.
3. Output D at Q. Do not write.
4. Output contents of array to Q. Do not write.
5. No operation.
6. No operation.
tn
tn + 1
K
Result from tn + 1 Clock
Data Output Q
D data appears
Q out from A
D data appears
Q out from A
Q is high–Z
Q is high–Z
Notes
1
2
3
4
5
6
ADDRESS & CONTROL
VALID
DATA INPUT D
DATA OUTPUT Q
VALID
PASS–THROUGH
PIPELINED READ ACCESS
VALID
MCM69Q618
4
MOTOROLA FAST SRAM