LTC1663 Ver la hoja de datos (PDF) - Linear Technology
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LTC1663 Datasheet PDF : 12 Pages
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TYPICAL PERFORMANCE CHARACTERISTICS
LTC1663
Load Regulation vs Output Current
1.0
0.8
VCC = VREF = 3V
VOUT = 1.5V
0.6
CODE = 512
TA = 25°C
0.4
0.2
0
–0.2
SOURCE
–0.4
SINK
–0.6
–0.8
–1.0
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
IOUT (mA)
1663 G07
Offset Error Voltage vs
Temperature
5
4
3
2
1
0
–1
–2
–3
–4
–5
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
80 100
1663 G08
Full-Scale Output Voltage vs
Temperature
2.510
2.508
2.506
REFERENCE SET TO
INTERNAL BANDGAP
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
80 100
1663 G09
PIN FUNCTIONS
SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged
by the SDA pin. High impedance pin while data is shifted
in. Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to VCC.
AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin.
Data is shifted into the SDA pin at the rising edges of the
clock. This high impedance pin requires a pull-up resistor
or current source to VCC.
VCC (Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ VCC
≤ 5.5V. Also used as the reference voltage input when the
part is programmed to use VCC as the reference.
AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
GND (Pin 7, Pin 2 on SOT-23): System Ground.
VOUT (Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered
rail-to-rail DAC output.
DEFINITIONS
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (ΔVOUT – LSB)/LSB
Where ΔVOUT is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the ana-
log output caused by AC coupling from the digital inputs
when they change state. The area of the glitch is specified
in (nV)(sec).
Full-Scale Error (FSE): The deviation of the actual full-scale
voltage from ideal. FSE includes the effects of offset and
gain errors (see Applications Information).
1663fd
5
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