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MT88L70 Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

Número de pieza
componentes Descripción
Fabricante
MT88L70
ZARLINK
Zarlink Semiconductor Inc ZARLINK
MT88L70 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MT88L70
Data Sheet
IN+ 1
IN- 2
GS 3
VRef 4
INH 5
PWDN 6
OSC1 7
OSC2 8
VSS 9
18 VDD
17 St/GT
16 ESt
15 StD
14 Q4
13 Q3
12 Q2
11 Q1
10 TOE
18 PIN PDIP/SOIC
IN+ 1
IN- 2
GS 3
VRef 4
INH 5
PWDN 6
NC 7
OSC1 8
OSC2 9
VSS 10
20 VDD
19 St/GT
18 ESt
17 StD
16 NC
15 Q4
14 Q3
13 Q2
12 Q1
11 TOE
20 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
18 20
Name
Description
11
22
IN+ Non-Inverting Op-Amp (Input).
IN- Inverting Op-Amp (Input).
33
GS Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
44
VRef Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Figure 5
and Figure 6).
55
INH Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and
D. This pin input is internally pulled down.
6 6 PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
7 8 OSC1 Clock (Input).
89
9 10
10 11
OSC2 Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
VSS
TOE
Ground (Input). 0 V typical.
Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled
up internally.
11- 12- Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the
14 15
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
15 17
16 18
StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below VTSt.
ESt Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
2
Zarlink Semiconductor Inc.

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