MT88L70 Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc
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MT88L70 Datasheet PDF : 16 Pages
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MT88L70
Data Sheet
AC Electrical Characteristics - VDD = 3.0 V+20%/-10%, VSS = 0 V, -40°C ≤ To ≤ +85°C, using Test Circuit shown in Figure 6.
Characteristics
Sym. Min. Typ.‡ Max. Units Conditions
1
Tone present detect time
tDP
5
11
14
ms Note 1
2 T Tone absent detect time
3
I
M
Tone duration accept
4 I Tone duration reject
N
5 G Interdigit pause accept
tDA
0.5
4
8.5 ms Note 1
tREC
40
ms Note 2
tREC
20
ms Note 2
tID
40
ms Note 2
6
Interdigit pause reject
tDO
20
ms Note 2
7
Propagation delay (St to Q)
tPQ
11
µs TOE=VDD
8 O Propagation delay (St to StD)
U
9 T Output data set up (Q to StD)
tPStD
tQStD
10
P
U
Propagation delay (TOE to Q ENABLE)
tPTE
T
S
11
Propagation delay (TOE to Q DISABLE) tPTD
20
5.0
50
130
µs TOE=VDD
µs TOE=VDD
ns load of 10 kΩ,
50 pF
ns load of 10 kΩ,
50 pF
12 P Power-up time
D
13 W Power-down time
N
tPU
30
ms Note 3
tPD
20
ms
14
Crystal/clock frequency
fC 3.5759 3.5795 3.5831 MHz
15 C Clock input rise time
L
16 O Clock input fall time
C
17 K Clock input duty cycle
tLHCL
tHLCL
DCCL 40
110 ns
110 ns
50
60
%
18
Capacitive load (OSC2)
CLO
15
pF
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Ext. clock
Ext. clock
Ext. clock
*NOTES:
1. Used for guard-time calculation purposes only and tested at -4 dBm.
2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums are
recommendations based upon network requirements.
3. With valid tone present at input, tPU equals time from PDWN going low until ESt going high.
11
Zarlink Semiconductor Inc.
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