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MT4LC4M4A1

4 MEG x 4 FPM DRAM

Micron Technology 

GENERAL DESCRIPTION

The 4 Meg x 4 DRAM is a randomly accessed, solid-

state memory containing 16,777,216 bits organized in

a x4 configuration. RAS# is used to latch the row

address (first 11 bits for 2K and first 12 bits for 4K). Once

the page has been opened by RAS#, CAS# is used to latch

the column address (the latter 11 bits for 2K and the

latter 10 bits for 4K; address pins A10 and A11 are “Don’t

Care”).

READ and WRITE cycles are selected with the WE#

input. A logic HIGH on WE# dictates read mode, while

a logic LOW on WE# dictates write mode. During a

WRITE cycle, data-in (D) is latched by the falling edge

of WE# or CAS#, whichever occurs last. If WE# goes

LOW prior to CAS# going LOW, the output pins

remain open (High- Z) until the next CAS# cycle,

regardless of OE#.

A logic HIGH on WE# dictates read mode, while a

logic LOW on WE# dictates write mode. During a

WRITE cycle, data-in (D) is latched by the falling edge

of WE# or CAS#, whichever occurs last. An EARLY

WRITE occurs when WE# is taken LOW prior to CAS#

falling. A LATE WRITE or READ-MODIFY-WRITE

occurs when WE# falls after CAS# is taken LOW. During

EARLY WRITE cycles, the data outputs (Q) will remain

High-Z regardless of the state of OE#. During LATE

WRITE or READ-MODIFY-WRITE cycles, OE# must be

taken HIGH to disable the data outputs prior to

applying input data. If a LATE WRITE or READ-

MODIFY-WRITE is attempted while keeping OE# LOW,

no WRITE will occur, and the data outputs will drive

read data from the accessed location.

The four data inputs and the four data outputs are

routed through four pins using common I/O, and pin

direction is controlled by WE# and OE#.

The MT4LC4M4B1 and MT4LC4M4A1 must be

refreshed periodically in order to retain stored data.

FAST PAGE MODE ACCESS

Page operations allow faster data operations (READ,

WRITE or READ-MODIFY-WRITE) within a row-

address-defined page boundary. The page cycle is al-

ways initiated with a row address strobed in by RAS#,

followed by a column address strobed in by CAS#.

4 MEG x 4

FPM DRAM

Additional columns may be accessed by providing valid

column addresses, strobing CAS# and holding RAS#

LOW, thus executing faster memory cycles. Returning

RAS# HIGH terminates the page mode of operation,

i.e., closes the page.

DRAM REFRESH

Preserve correct memory cell data by maintaining

power and executing any RAS# cycle (READ, WRITE)

or RAS# REFRESH cycle (RAS#-ONLY, CBR, or HID-

DEN) so that all combinations of RAS# addresses (2,048

for 2K and 4,096 for 4K) are executed within tREF

(MAX), regardless of sequence. The CBR and SELF

REFRESH cycles will invoke the internal refresh counter

for automatic RAS# addressing.

An optional self refresh mode is also available the

“S” version. The self refresh feature is initiated by

performing a CBR REFRESH cycle and holding RAS#

LOW for the specified tRASS. The “S” option allows the

user the choice of a fully static, low-power data reten-

tion mode or a dynamic refresh mode at the extended

refresh period of 128ms, or 31.25µs per row for a 4K

refresh and 62.5µs per row for a 2K refresh, when using

a distributed CBR REFRESH. This refresh rate can be

applied during normal operation, as well as during a

standby or battery backup mode.

The self refresh mode is terminated by driving RAS#

HIGH for a minimum time of tRPS. This delay allows for

the completion of any internal refresh cycles that may

be in process at the time of the RAS# LOW-to-HIGH

transition. If the DRAM controller uses a distributed

CBR refresh sequence, a burst refresh is not required

upon exiting self refresh. However, if the DRAM con-

troller utilizes RAS#-ONLY or burst CBR refresh se-

quence, all rows must be refreshed with a refresh rate of

tRC minimum prior to resuming normal operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a

memory cycle and decreases chip current to a reduced

standby level. The chip is preconditioned for the next

cycle during the RAS# HIGH time.

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

2

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000, Micron Technology, Inc.

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