M48T18-100PC Ver la hoja de datos (PDF) - STMicroelectronics
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M48T18-100PC Datasheet PDF : 73 Pages
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M48T08, M48T18
Table 4. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition
Min
Max
CIN
Input Capacitance
VIN = 0V
10
CIO (2)
Input / Output Capacitance
VOUT = 0V
10
Notes: 1. Effective capacitance calculated from the equation C = I∆t/∆V with ∆V = 3V and power supply at 5V.
2. Outputs deselected
Unit
pF
pF
Table 5. DC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
Test Condition
ILI (1)
ILO (1)
Input Leakage Current
Output Leakage Current
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
ICC
ICC1 (2)
Supply Current
Supply Current (Standby) TTL
Outputs open
E1 = VIH, E2 = VIL
ICC2 (2)
VIL(3)
Supply Current (Standby) CMOS
Input Low Voltage
E1 = VCC – 0.2V,
E2 = VSS + 0.2V
VIH
Input High Voltage
Output Low Voltage
VOL
Output Low Voltage (INT) (4)
IOL = 2.1mA
IOL = 0.5mA
VOH
Output High Voltage
IOH = –1mA
Notes: 1. Outputs Deselected.
2. Measured with Control Bits set as follows: R = ’1’; W, ST, FT = ’0’.
3. Negative spikes of –1V allowed for up to 10ns once per Cycle.
4. The INT pin is Open Drain.
Min
Max
±1
±5
80
3
3
–0.3
2.2
2.4
0.8
VCC + 0.3
0.4
0.4
Unit
µA
µA
mA
mA
mA
V
V
V
V
V
Table 6. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70°C)
Symbol
Parameter
VPFD
Power-fail Deselect Voltage (M48T08)
VPFD Power-fail Deselect Voltage (M48T18)
VSO
Battery Back-up Switchover Voltage
tDR(2)
Expected Data Retention Time
Notes: 1. All voltages referenced to VSS.
2. @ 25°C
Min
Typ
Max
Unit
4.5
4.6
4.75
V
4.2
4.3
4.5
V
3.0
V
10
YEARS
DESCRIPTION (cont’d)
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting.The SNAPHAT housing is keyed to
prevent reverse insertion.
The SO and battery packages are shipped sepa-
rately in plastic anti-static tubes. The SO package
is also available to ship in Tape & Reel form. For
the 28 lead SO, the battery package (i.e.
SNAPHAT) part number is ”M4T28-BR12SH1”.
As Figure 3 shows, the static memory array and the
quartz controlled clock oscillator of the M48T08,18
are integrated on one silicon chip. The two circuits
are interconnected at the upper eight memory lo-
cations to provide user accessible BYTEWIDE™
clock information in the bytes with addresses
1FF8h-1FFFh. The clock locations contain the
year, month, date, day, hour, minute, and second in
4/18
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