M95640-RMN5 Ver la hoja de datos (PDF) - STMicroelectronics

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M95640-RMN5

64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

M95640, M95320, M95160, M95080

Table 4. Instruction Set

Instruc

tion

Description

Instruction

Format

WREN Set Write Enable Latch

0000 0110

WRDI Reset Write Enable Latch

0000 0100

RDSR Read Status Register

0000 0101

WRSR Write Status Register

0000 0001

READ Read Data from Memory Array 0000 0011

WRITE Write Data to Memory Array 0000 0010

Table 5. Status Register Format

b7

b0

SRWD X X X BP1 BP0 WEL WIP

Note: 1. SRWD, BP0 and BP1 are Read and write bits.

2. WEL and WIP are Read only bits.

operation. A ’1’ indicates that a write is in progress,

and a ’0’ that no write is in progress.

The Write Enable Latch (WEL) bit indicates the

status of the write enable latch. It, too, is read-only.

Its value can only be changed by one of the events

listed in the previous paragraph, or as a result of

executing WREN or WRDI instruction. It cannot be

changed using a WRSR instruction. A ’1’ indicates

that the latch is set (the forthcoming Write instruc-

tion will be executed), and a ’0’ that it is reset (and

any forthcoming Write instructions will be ignored).

The Block Protect (BP0 and BP1) bits indicate the

amount of the memory that is to be write-protect-

ed. These two bits are non-volatile. They are set

using a WRSR instruction.

During a Write operation (whether it be to the

memory area or to the status register), all bits of

the status register remain valid, and can be read

using the RDSR instruction. However, during a

Write operation, the values of the non-volatile bits

(SRWD, BP0, BP1) become frozen at a constant

value. The updated value of these bits becomes

available when a new RDSR instruction is execut-

ed, after completion of the write cycle. On the oth-

er hand, the two read-only bits (WEL, WIP) are

dynamically updated during internal write cycles.

Using this facility, it is possible to poll the WIP bit

to detect the end of the internal write cycle.

Write Status Register (WRSR)

The format of the WRSR instruction is shown in

Figure 7. After the instruction and the eight bits of

the status register have been latched-in, the inter-

nal Write cycle is triggered by the rising edge of

the S line. This must occur after the falling edge of

the 16th clock pulse, and before the rising edge of

the 17th clock (as indicated in Figure 7), otherwise

the internal write sequence is not performed.

The WRSR instruction is used for the following:

s to select the size of memory area that is to be

write-protected

s to select between SPM (Software Protected

Mode) and HPM (Hardware Protected Mode).

The size of the write-protection area applies equal-

ly in SPM and HPM. The BP1 and BP0 bits of the

status register have the appropriate value (see Ta-

ble 6) written into them after the contents of the

protected area of the EEPROM have been written.

The initial delivery state of the BP1 and BP0 bits is

00, indicating a write-protection size of 0.

Software Protected Mode (SPM)

The act of writing a non-zero value to the BP1 and

BP0 bits causes the Software Protected Mode

(SPM) to be started. All attempts to write a byte or

page in the protected area are ignored, even if the

Write Enable Latch is set. However, writing is still

allowed in the unprotected area of the memory ar-

Figure 6. RDSR: Read Status Register Sequence

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C

INSTRUCTION

D

STATUS REG. OUT

STATUS REG. OUT

HIGH IMPEDANCE

Q

76543210765432107

MSB

MSB

MSB

AI02031

6/19

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