M95640-RMN5 Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

M95640-RMN5

64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

Figure 5. Block Diagram

HOLD

W

S

C

D

Q

Control Logic

I/O Shift Register

M95640, M95320, M95160, M95080

High Voltage

Generator

Address Register

and Counter

Data

Register

An - 31

Status

Register

An

Size of the

Read only

EEPROM

area

0000h

32 Bytes

X Decoder

001Fh

Note: 1. The cell An represents the byte at the highest address in the memory

AI01792C

As soon as the WREN or WRDI instruction is re-

ceived, the memory device first executes the in-

struction, then enters a wait mode until the device

is deselected.

Read Status Register (RDSR)

The RDSR instruction allows the status register to

be read, and can be sent at any time, even during

a Write operation. Indeed, when a Write is in

progress, it is recommended that the value of the

Write-In-Progress (WIP) bit be checked. The value

in the WIP bit (whose position in the status register

is shown in Table 5) can be continuously polled,

before sending a new WRITE instruction. This can

be performed in one of two ways:

s Repeated RDSR instructions (each one

consisting of S being taken low, C being clocked

8 times for the instruction and 8 times for the

read operation, and S being taken high)

s A single, prolonged RDSR instruction

(consisting of S being taken low, C being

clocked 8 times for the instruction and kept

running for repeated read operations), as

shown in Figure 6.

The Write-In-Process (WIP) bit is read-only, and

indicates whether the memory is busy with a Write

5/19

Share Link: