¡ Semiconductor
FEDL9000B-01
MSM9000B-xx
Serial interface
Parameter
Symbol
(VDD = 2.5 to 3.3 V, VBI = 3 to 5.5 V, Ta = –30 to +85°C)
Condition
Min.
Max.
Unit
CS or C/D setup time
tSAS
—
100
—
ns
CS or C/D hold time
tSAH
—
20
—
ns
SI setup time
tIS
—
100
—
ns
SI hold time
tIH
—
SHT high-level pulse width
tWSHH
—
SHT low-level pulse width
tWSHL
—
SHT clock cycle time
tSYS
—
20
—
ns
100
—
ns
100
—
ns
400
—
ns
SO ON delay time
tON
CL= 50 pF
—
200
ns
SO output delay time
tDS
CL= 50 pF
0
200
ns
SO OFF delay time
tOFF
—
—
100
ns
BUSY delay time
WR setup time
WR low-level pulse width
RESET pulse width
tBUSY
tSHS
tWWL
tWRE
CL= 50 pF
—
—
—
—
200
ns
200
—
ns
120
—
ns
2.0
—
ms
Rise and fall time of external
clock
tr, tf
—
—
100
ns
Note: The values in this table are assured when the chip is not exposed to light.
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