MSM80C85 Ver la hoja de datos (PDF) - Oki Electric Industry

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Fabricante

MSM80C85

8-Bit CMOS MICROPROCESSOR

Oki Electric Industry 

¡ Semiconductor

MSM80C85AHRS/GS/JS

FUNCTIONAL DESCRIPTION

The MSM80C85AH is a complete 8-bit parallel central processor. It is designed with silicon gate

C-MOS technology and requires a single +5 volt supply. Its basic clock speed is 5 MHz, thus

improving on the present MSM80C85A's performance with higher system speed and power

down mode. Also it is designed to fit into a minimum system of two IC's: The CPU

(MSM80C85AH), and a RAM/IO (MSM81C55-5)

The MSM80C85AH has twelve addressable 8-bit register pairs. Six others can be used

interchangeably as 8-bit registers or 16-bit register pairs. The MSM80C85AH register set is as

follows:

Mnemonic

Register

Contents

ACC or A

Accumulator

8-bits

PC

Program Counter

16-bit address

BC, DE, HL

General-Purpose Registers; data pointer (HL)

8-bit ¥ 6 or 16-bits ¥ 3

SP

Stack Pointer

16-bit address

Flags or F

Flag Register

5 flags (8-bit space)

The MSM80C85AH uses a multiplexed Data Bus. The address is spilt between the higher 8-bit

Address Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a

machine cycle the low order address is sent out on the Address/Data Bus. These lower 8-bits

may be latched externally by the Address Latch Enable signal (ALE). During the rest of the

machine cycle the data bus is used for mamory or I/O data.

The MSM80C85AH provides RD, WR, S0, S1, and IO/M signals for bus control. An Interrupt

Acknowledge signal (INTA) is also provided. Hold and all Interrupts are synchronized with

the processor's internal clock. The MSM80C85AH also provides Serial Input Data (SID) and

Serial Output Data (SOD) lines for a simple serial interface.

In addition to these features, the MSM80C85AH has three maskable, vector interrupt pins, one

nonmaskable TRAP interrupt and power down mode with HALT and HOLD.

INTERRUPT AND SERIAL I/O

The MSM80C85AH has 5 interrupt inputs: INTR, RST 5.5 RST 6.5, RST 7.5, and TRAP. INTR is

identical in function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has

a programmable mask. TRAP is also a RESTART interrupt but it is nonmaskable.

The three maskable interrupts cause the internal execution of RESTART ( saving the program

counter in the stack branching to the RESTART address) it the interrupts are enable and if the

interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART

vector independent of the state of the interrupt enable or masks. (See Table 1.)

There are two different types of inputs in the restart interrupt. RST 5.5 and RST 6.5 are high

level-sensitive like INTR (and INT on the 8080A) and are recognized with the same timing as

INTR. RST 7.5 is rising edge-sensitive.

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