MSM80C85 Ver la hoja de datos (PDF) - Oki Electric Industry
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MSM80C85 Datasheet PDF : 29 Pages
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MSM80C85AHRS/GS/JS
Table 3 MSM80C85AH Machine State Chart
Machine State
T1
T2
TWAIT
T3
T4
T5
T6
TRESET
THALT
THOLD
S1, S0
¥
¥
¥
¥
1
1
1
¥
0
¥
Status & Buses
IO/M
A8 – A15
¥
¥
¥
¥
¥
¥
¥
¥
0 (2)
¥
0 (2)
¥
0 (2)
¥
TS
TS
TS
TS
TS
TS
AD0 – AD7
¥
¥
¥
¥
TS
TS
TS
TS
TS
TS
RD, WR
1
¥
¥
¥
1
1
1
TS
TS
TS
0 = Logic "0"
1 = Logic "1"
TS = High Impedance
¥ = Unspecified
Notes: (1) ALE not generated during 2nd and 3rd machine cycles of DAD instruction.
(2) IO/M = 1 during T4 - T6 of INA machine cycle.
Control
INTA
1
¥
¥
¥
1
1
1
1
1
1
ALE
1 (1)
0
0
0
0
0
0
0
0
0
CLK
A8-15
AD0-7
ALE
RD
WR
IO/M
STATUS
M1
T1
T2
T3
T4
PCH (High Order Address)
PCL
(Low Order
Address)
Data from Memory
(Instruction)
S1S0(Fetch)
M2
M3
T1
T2
T3
T1
T2
T3
T
(PC+1)H
(PC+1)L1
Data from Memory
(I/O Port Address)
IO Port
IO Port
Data to Memory
or Peripheral
10 (Read)
01 Write
11
Figure 5 MSM80C85AH Basic System Timing
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