RM5261A-350-HI Ver la hoja de datos (PDF) - PMC-Sierra

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RM5261A-350-HI

Microprocessor with 64-Bit System Bus

PMC-Sierra 

RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet

Preliminary

Table of Contents

Legal Information ...........................................................................................................................2

Revision History .............................................................................................................................3

Document Conventions .................................................................................................................4

Table of Contents ..........................................................................................................................5

List of Figures ................................................................................................................................7

List of Tables ................................................................................................................................. 8

1 Features .................................................................................................................................. 9

2 Block Diagram .......................................................................................................................10

3 Hardware Overview ...............................................................................................................11

3.1 Superscalar Dispatch ...................................................................................................11

3.2 CPU Registers .............................................................................................................11

3.3 Integer Unit ..................................................................................................................11

3.4 Pipeline ........................................................................................................................12

3.5 Register File .................................................................................................................12

3.6 ALU ..............................................................................................................................12

3.7 Integer Multiply/Divide ..................................................................................................12

3.8 Floating-Point Co-Processor ........................................................................................13

3.9 Floating-Point Unit .......................................................................................................13

3.10 Floating-Point General Register File ............................................................................15

3.11 System Control Co-processor (CP0) ............................................................................16

3.12 System Control Co-Processor Registers .....................................................................16

3.13 Virtual to Physical Address Mapping ............................................................................17

3.14 Joint TLB ......................................................................................................................18

3.15 Instruction TLB .............................................................................................................18

3.16 Data TLB ......................................................................................................................19

3.17 Cache Memory .............................................................................................................19

3.18 Instruction Cache .........................................................................................................19

3.19 Data Cache ..................................................................................................................19

3.20 Write buffer ..................................................................................................................21

3.21 System Interface ..........................................................................................................21

3.22 System Address/Data Bus ...........................................................................................22

3.23 System Command Bus ................................................................................................22

3.24 Handshake Signals ......................................................................................................22

3.25 Non-overlapping System Interface ...............................................................................23

3.26 Enhanced Write Modes ................................................................................................24

3.27 External Requests ........................................................................................................24

3.28 Interrupt Handling ........................................................................................................25

3.29 Standby Mode ..............................................................................................................25

3.30 JTAG Interface .............................................................................................................25

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

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Document ID: PMC-202240, Issue 2

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