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IDT49C466PQF

64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

Integrated Device Technology 

IDT49C466/A Flow-thruEDC™

ERROR DETECTION AND CORRECTION UNIT

COMMERCIAL TEMPERATURE RANGES

R/W FIFO Operation At Boundaries

In the 49C466 the write pointer is incremented on every

FIFO write. Similarly the read pointer is incremented on every

FIFO read. In most cases on a FIFO read, the last data read

remains at the output of the FIFO, until the read pointer is

further incremented. On the last (the write that fills the FIFO)

FIFO write after the FIFO read, however, this last read data is

overwritten by the 16th write following the empty condition and

consequently the data at the FIFO output is liable to change.

The situation is depicted in the diagram below.

overwritten and the FIFO output changes from AA to the data

just written, namely QQ.

This operation needs to be taken into account in the design

of the system. In case of a burst operation where FIFO data

is output at a much slower rate than the rate at which data is

input and the full flag is expected to inhibit further writes, the

user cannot expect the FIFO output to remain static through

the 16th write of the burst. If this is a requisite to the design,

the FIFO output should be latched. In the case of the write

FIFO this can be accomplished on-chip by latching the FIFO

reset

WRITE1

(data = AA)

WRITE1

(data = BB)

WRITE2

(data =CC)

WRITE15

(data = PP)

WRITE16

(data = QQ)

WP

RP

WP

FIFO

(empty)

FIFO

RP

WP

FIFO

(empty)

RP

WP

FIFO

RP

WP

FIFO

RP

WP

FIFO

RP

WP

FIFO

(full)

READ1

(data = AA)

No READs

(data = AA)

No READs

(data = AA)

No READs

(data = AA)

No READs

(data = QQ)

Figure 2. R/W FIFO Operation

The diagram in figure 2 progresses from the FIFO

initialization(reset) through a sequence of write operations.

After the first write, a read is executed which establishes the

data at the FIFO output(AA). On the last write to the FIFO(the

write that fills the FIFO), the location of the last read data is

output in the SD output latch. For the read FIFO, the FIFO

output must be latched externally to accomplish the same

thing, since there is no latch on-chip following the FIFO. If this

cannot be done and the situation described above is expected

to occur in normal operation, the write must be inhibited one

cycle before the FIFO becomes full.

11.7

9

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