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MSC7116
(Rev.:2007)

Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Freescale Semiconductor 

Table of Contents

1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.1 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4

1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6

2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.2 Recommended Operating Conditions. . . . . . . . . . . . . .18

2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .19

2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19

2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .41

3.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . .41

3.2 Power Supply Design Considerations. . . . . . . . . . . . . .42

3.3 Estimated Power Usage Calculations. . . . . . . . . . . . . .44

3.4 Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

3.5 DDR Memory System Guidelines . . . . . . . . . . . . . . . . .49

4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

List of Figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

MSC7116 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3

MSC7116 Molded Array Process-Ball Grid Array

(MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4

MSC7116 Molded Array Process-Ball Grid Array

(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5

Timing Diagram for a Reset Configuration Write . . . . 25

Figure 5. DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 26

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

Figure 31.

Figure 32.

Figure 33.

DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 27

DDR DRAM AC Test Load . . . . . . . . . . . . . . . . . . . . . 28

TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . . 28

TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . 29

Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . 29

Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . 30

Asynchronous Input Signal Timing . . . . . . . . . . . . . . . 30

Serial Management Channel Timing . . . . . . . . . . . . . 31

Read Timing Diagram, Single Data Strobe . . . . . . . . 33

Read Timing Diagram, Double Data Strobe . . . . . . . . 33

Write Timing Diagram, Single Data Strobe. . . . . . . . . 34

Write Timing Diagram, Double Data Strobe . . . . . . . . 34

Host DMA Read Timing Diagram, HPCR[OAD] = 0 . . 35

Host DMA Write Timing Diagram, HPCR[OAD] = 0 . . 35

I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36

UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 37

EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . 38

Test Clock Input Timing Diagram . . . . . . . . . . . . . . . . 39

Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . 40

Test Access Port Timing Diagram . . . . . . . . . . . . . . . 40

TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 40

Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 43

PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . 43

SSTL Termination Techniques . . . . . . . . . . . . . . . . . . 49

SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11

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Freescale Semiconductor

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