PM5356-BI Ver la hoja de datos (PDF) - PMC-Sierra
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PM5356-BI Datasheet PDF : 307 Pages
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RELEASED
S/UNI-622-MAX
DATASHEET
PMC-1980589
ISSUE 6
PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
SATURN USER NETWORK INTERFACE (622-MAX)
LIST OF FIGURES
FIGURE 1: TYPICAL STS-12C/STM-4-4C ATM (UTOPIA LEVEL 2) SWITCH PORT APPLICATION ........11
FIGURE 2: TYPICAL STS-12C/STM-4-4C ATM (UTOPIA LEVEL 3) SWITCH PORT APPLICATION ........11
FIGURE 3: TYPICAL STS-12C/STM-4-4C S/UNI-622-MAX JITTER TOLERANCE .................................. 42
FIGURE 4: POINTER INTERPRETATION STATE DIAGRAM.................................................................... 48
FIGURE 5: CELL DELINEATION STATE DIAGRAM.................................................................................. 53
FIGURE 6: HCS VERIFICATION STATE DIAGRAM.................................................................................. 55
FIGURE 7: INPUT OBSERVATION CELL (IN_CELL) .............................................................................. 235
FIGURE 8: OUTPUT CELL (OUT_CELL) ................................................................................................ 235
FIGURE 9: BIDIRECTIONAL CELL (IO_CELL) ....................................................................................... 236
FIGURE 10: LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ......................................... 236
FIGURE 11: ATM MAPPING INTO THE STS-12C/STM-4-4C SPE.......................................................... 237
FIGURE 12: STS-12C/STM-4-4C OVERHEAD ....................................................................................... 238
FIGURE 13: 16-BIT WIDE, 27 WORD ATM CELL STRUCTURE............................................................. 242
FIGURE 14: 8-BIT WIDE, 54 BYTE ATM CELL STRUCTURE................................................................. 243
FIGURE 15: CLOCKING STRUCTURE ................................................................................................... 247
FIGURE 16: LINE LOOPBACK MODE .................................................................................................... 249
FIGURE 17: SERIAL DIAGNOSTIC LOOPBACK MODE......................................................................... 250
FIGURE 18: PARALLEL DIAGNOSTIC LOOPBACK MODE ................................................................... 250
FIGURE 19: PATH DIAGNOSTIC LOOPBACK MODE ............................................................................ 251
FIGURE 20: DATA DIAGNOSTIC LOOPBACK MODE ............................................................................ 251
FIGURE 21: 1+1 APS ARCHITECTURE .................................................................................................. 252
FIGURE 22: BOUNDARY SCAN ARCHITECTURE................................................................................. 254
FIGURE 23: TAP CONTROLLER FINITE STATE MACHINE ................................................................... 255
FIGURE 24: POWER SUPPLY FILTERING AND DECOUPLING ............................................................ 261
FIGURE 25: POWER SUPPLY COMPONENT LAYOUT ......................................................................... 262
FIGURE 26: INTERFACING S/UNI-622-MAX PECL PINS TO 3.3V DEVICES........................................ 263
FIGURE 27: INTERFACING S/UNI-622-MAX PECL PINS TO 5.0V DEVICES........................................ 264
FIGURE 28: IN FRAME DECLARATION TIMING .................................................................................... 267
FIGURE 29: OUT OF FRAME DECLARATION TIMING .......................................................................... 268
FIGURE 30: PARALLEL TRANSMIT INTERFACE TIMING ..................................................................... 268
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE v
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