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TC1321EUA
(Rev.:2002)

10-Bit Digital-to-Analog Converter with Two-Wire Interface

Microchip Technology 

TC1321

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings*

Supply Voltage (VDD) ............................................. +6V

Voltage on any Pin ... (GND – 0.3V) to (VDD + 0.3V)

Current on any Pin ............................................ ±50mA

Package Thermal Resistance (θJA)............ 330°C C/W

Operating Temperature (TA)........................ See Below

Storage Temperature (TSTG) .............. -65°C to +150°C

*Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device. These

are stress ratings only and functional operation of the device

at these or any other conditions above those indicated in the

operation sections of the specifications is not implied.

Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability.

TC1321 ELECTRICAL SPECIFICATIONS

Electrical Characteristics: VDD = 2.7V to 5.5V, -40°C ≤ TA ≤ +85°C, VREF = 1.2 unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Power Supply

VDD

Supply Voltage

IDD

Operating Current

IDD-STANDBY Standby Supply Current

2.7

—

5.5

V

—

350

500

mA VDD = 5.5V, VREF = 1.2V

Serial Port Inactive (Note 1)

—

0.1

1

µA VDD = 3.3V

Serial Port Inactive (Note 1)

Static Performance - Analog Section

Resolution

—

INL

Integral Non-Linearity at FS, TA = +25°C —

FSE

Full Scale Error

—

DNL

Differential Non-Linearity, TA = +25°C

-1

VOS

Offset Error at VOUT

—

TCVOS

Offset Error Tempco at VOUT

—

PSRR

Power Supply Rejection Ratio

—

VREF

Voltage Reference Range

0

IREF

Reference Input Leakage Current

—

VSW

Voltage Swing

0

ROUT

Output Resistance @ VOUT

—

IOUT

Output Current (Source or Sink)

—

ISC

Output Short-Circuit Current

—

VDD = 5.5V

—

Dynamic Performance

SR

Voltage Output Slew Rate

—

tSETTLE

tWU

Output Voltage Full Scale Settling Time —

Wake-up Time

—

Digital Feed Through and Crosstalk

—

—

—

—

—

±0.3

10

80

—

—

—

5.0

2

30

20

10

±4.0

±3

+2

±8

—

—

VDD – 1.2

±1.0

VREF

—

—

50

50

0.8

—

10

—

20

—

5

—

Serial Port Interface

VIH

Logic Input High

VIL

Logic Input Low

VOL

SDA Output Low

2.4

—

VDD

—

—

0.6

—

—

0.4

—

—

0.6

CIN

Input Capacitance SDA, SCL

—

5

0.4

ILEAK

I/O Leakage

—

—

±1.0

Note 1: SDA and SCL must be connected to VDD or GND.

2: Measured at VOUT ≥ 50mV referred to GND to avoid output buffer clipping.

Bits

LSB

%FS

LSB

mV

µv/°C

dB

V

µA

V

Ω

mA

mA

mA

(Note 2)

All Codes (Note 2)

(Note 2)

VDD at DC

VREF ≤ (VDD – 1.2V)

ROUT (Ω)

Source

Sink

V/µs

µsec

µs

nV-s

SDA = VDD, SCL = 100kHz

V

—

V IOL = 3mA (Sinking Current)

V IOL = 6mA

pF

µA

© 2002 Microchip Technology Inc.

DS21387B-page 3

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