AD7814 Ver la hoja de datos (PDF) - Analog Devices
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AD7814 Datasheet PDF : 8 Pages
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AD7814–SPECIFICATIONS1
(TA = TMIN to TMAX, VDD = 2.7 V to 5.5 V, unless otherwise noted.)
Parameter
Min Typ
Max Unit Test Conditions/Comments
TEMPERATURE SENSOR AND ADC
Accuracy
Resolution
Update Rate, tR
Temperature Conversion Time
± 2.0
10
400
25
± 2.0 °C
± 2.5 °C
± 3.5 °C
TA = 0°C to 85°C. VDD = 3 V to 5.5 V2
TA = –40°C to 0°C. VDD = 3 V to 5.5 V2
TA = –55°C to +125°C. VDD = 3 V to 5.5 V
Bits
µs
µs
SUPPLIES
Supply Voltage
Supply Current
Normal Mode
Shutdown Mode (VDD = 5 V)
Shutdown Mode (VDD = 3 V)
Power Dissipation
Power Dissipation
1 sps
10 sps
100 sps
2.7
250
1.23
0.43
80
3.7
3.9
5.8
5.5
V
400 µA
3
µA
1
µA
µW
µW
µW
µW
DIGITAL INPUT3
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUT3
Output High Voltage, VOH
Output Low Voltage, VOL
Output Capacitance, COUT
2.4
VDD – 0.3 V
V
0.8
V
±1
µA
10
pF
0.4
V
50
pF
NOTES
1All specifications apply for –55°C to +125°C unless otherwise stated.
2For VDD = 2.7 V to 3 V and TA = –40°C to +85°C, the typical temperature error is ± 2°C.
3Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
For Specified Performance
VDD = 3 V. Using Normal Mode
VDD = 3 V. Using Shutdown Mode
VIN = 0 V to VDD
All Digital Inputs
ISOURCE = ISINK = 200 µA
IOL = 200 µA
TIMING CHARACTERISTICS1, 2, 3
(TA = TMIN to TMAX, VDD = 2.7 V to 5.5 V, unless otherwise noted.)
Parameter
Limit
Unit
Comments
t1
0
ns min
CS to SCLK Setup Time
t2
50
ns min
SCLK High Pulse Width
t3
50
ns min
SCLK Low Pulse Width
t44
35
ns max
Data Access Time After SCLK Falling Edge
t5
20
ns min
Data Setup Time Prior to SCLK Rising Edge
t6
0
ns min
Data Hold Time After SCLK Rising Edge
t7
0
ns min
CS to SCLK Hold Time
t84
40
ns max
CS to DOUT High Impedance
NOTES
1Guaranteed by design and characterization, not production tested.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
3See Figure 2.
4Measured with the load circuit of Figure 1.
Specifications subject to change without notice.
–2–
REV. E
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