MPC9608 Ver la hoja de datos (PDF) - Motorola => Freescale

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componentes Descripción

Fabricante

MPC9608

1:10 LVCMOS Zero Delay Clock Buffer

Motorola => Freescale 

Freescale Semiconductor, Inc.

MPC9608

tSK(O)

VCC

VCC ÷ 2

GND

VCC

VCC ÷ 2

GND

The pin-to-pin skew is defined as the worst case difference in propa-

gation delay between any similar delay path within a single device.

Figure 9. Output-to-output Skew tSK(O)

CCLK

FB_IN

t(∅)

VCC

VCC ÷ 2

GND

VCC

VCC ÷ 2

GND

Figure 10. Propagation delay (tPD, static phase offset)

test reference

VCC

VCC ÷ 2

GND

tP

T0

DC = tP/T0 x 100%

The time from the PLL controlled edge to the non controlled edge, di-

vided by the time between PLL controlled edges, expressed as a per-

centage.

Figure 11. Output Duty Cycle (DC)

CCLK

FB_IN

TJIT(∅) = |T0 - T1 mean|

The deviation in t0 for a controlled edge with respect to a t0 mean in a

random sample of cycles.

Figure 12. I/O Jitter

TN

TN + 1

TJIT(CC) = |TN -TN + 1|

The variation in cycle time of a signal between adjacent cycles, over a

random sample of adjacent cycle pairs.

Figure 13. Cycle-to-cycle Jitter

TJIT(PER) = |TN - 1/f0|

T0

The deviation in cycle time of a signal with respect to the ideal period

over a random sample of cycles.

Figure 14. Period Jitter

VCC = 3.3 V

2.4

0.55

tF

tR

Figure 15. Output Transition Time Test Reference

CCLK

CLK_STOP

ts

tH

VCC

VCC ÷ 2

GND

VCC

VCC ÷ 2

GND

Figure 16. Setup and Hold Time (ts, tH) Test Reference

TIMING SOLUTIONS

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