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MPC9608

1:10 LVCMOS Zero Delay Clock Buffer

Motorola => Freescale 

MPC9608

Freescale Semiconductor, Inc.

APPLICATIONS INFORMATION

Power Supply Filtering

The MPC9608 is a mixed analog/digital product. Its analog

circuitry is naturally susceptible to random noise, especially if

this noise is seen on the power supply pins. Random noise on

the VCCA (PLL) power supply impacts the device characteris-

tics, for instance I/O jitter. The MPC9608 provides separate

power supplies for the output buffers (VCC) and the

phase-locked loop (VCCA) of the device. The purpose of this de-

sign technique is to isolate the high switching noise digital out-

puts from the relatively sensitive internal analog phase-locked

loop. In a digital system environment where it is more difficult to

minimize noise on the power supplies a second level of isolation

may be required. The simple but effective form of isolation is a

power supply filter on the VCCA pin for the MPC9608. Figure 3

illustrates a typical power supply filter scheme. The MPC9608

frequency and phase stability is most susceptible to noise with

spectral content in the 100 kHz to 20 MHz range. Therefore the

filter should be designed to target this range. The key parame-

ter that needs to be met in the final filter design is the DC volt-

age drop across the series filter resistor RF. From the data

sheet the ICCA current (the current sourced through the VCCA

pin) is typically 4 mA (8 mA maximum), assuming that a mini-

mum of 3.125 V must be maintained on the VCCA pin. The re-

sistor RF shown in Figure 3 “VCCA Power Supply Filter” must

have a resistance of 9 – 10 Ω (VCC = 3.3 V) to meet the voltage

drop criteria.

RF = 9-10 Ω for VCC = 3.3 V

CF = 1 µF for VCC = 3.3 V

RF

VCC

VCCA

CF

10 nF

MPC9608

(isolated power and grounds and fully differential PLL), there

still may be applications in which overall performance is being

degraded due to system power supply noise. The power supply

filter schemes discussed in this section should be adequate to

eliminate power supply noise related problems in most designs.

Using the MPC9608 in Zero-delay Applications

Nested clock trees are typical applications for the

MPC9608. Designs using the MPC9608, as LVCMOS PLL

fanout buffer with zero insertion delay, will show significantly

lower clock skew than clock distributions developed from

CMOS fanout buffers. The external feedback option of the

MPC9608 clock driver allows for its use as a zero delay buffer.

By using the QFB output as a feedback to the PLL the

propagation delay through the device is virtually eliminated.

The PLL aligns the feedback clock output edge with the clock

input reference edge resulting in a near zero delay through the

device. The maximum insertion delay of the device in

zero-delay applications is measured between the reference

clock input and any output. This effective delay consists of the

static phase offset, I/O jitter (phase or long-term jitter), feedback

path delay and the output-to-output skew error relative to the

feedback output.

Calculation of Part-to-Part Skew

The MPC9608 zero delay buffer supports applications

where critical clock signal timing can be maintained across sev-

eral devices. If the reference clock inputs of two or more

MPC9608 are connected together, the maximum overall timing

uncertainty from the common CCLK input to any output is:

tSK(PP) = t(∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅) . CF

This maximum timing uncertainty consists of 4 compo-

nents: static phase offset, output skew, feedback board trace

delay, and I/O (phase) jitter:

VCC

33...100 nF

CCLKCommon

-t(∅)

tPD,LINE(FB)

Figure 3. VCCA Power Supply Filter

The minimum values for RF and the filter capacitor CF are

defined by the required filter characteristics: the RC filter should

provide an attenuation greater than 40 dB for noise whose

spectral content is above 100 kHz. In the example RC filter

shown in Figure 3 “VCCA Power Supply Filter”, the filter cut-off

frequency is around 3-5 kHz and the noise attenuation at

100 kHz is better than 42 dB.

As the noise frequency crosses the series resonant point

of an individual capacitor, its overall impedance begins to look

inductive and thus increases with increasing frequency. The

parallel capacitor combination shown ensures that a low imped-

ance path to ground exists for frequencies well above the band-

width of the PLL. Although the MPC9608 has several design

features to minimize the susceptibility to power supply noise

QFBDevice 1

tJIT(∅)

Any QDevice 1

+tSK(O)

QFBDevice2

+t(∅)

tJIT(∅)

Any QDevice 2

+tSK(O)

Max. skew

tSK(PP)

Figure 4. MPC9608 maximum device-to-device skew

6

For More Information On This Product,

TIMING SOLUTIONS

Go to: www.freescale.com

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