MPC9447 Ver la hoja de datos (PDF) - Motorola => Freescale
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MPC9447 Datasheet PDF : 12 Pages
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Freescale Semiconductor, Inc.
MPC9447
Table 4. Absolute Maximum Ratingsa
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
VIN
VOUT
IIN
IOUT
TS
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
-0.3
3.9
V
-0.3
VCC + 0.3
V
-0.3
VCC + 0.3
V
±20
mA
±50
mA
-65
125
°C
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics (VCC = 3.3V ± 5%, TA = 40°C to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
2.0
VCC + 0.3
V LVCMOS
VIL
Input Low Voltage
VOH
Output High Voltage
--0.3
0.8
V LVCMOS
2.4
V
IOH = -24 mAa
VOL
Output Low Voltage
0.55
0.30
V
IOL = 24 mA
V
IOL = 12 mA
ZOUT
IIN
ICCQ
Output Impedance
Input Currentb
Maximum Quiescent Supply Currentc
17
Ω
±300
µA VIN = VCC or GND
2.0
mA All VCC Pins
a. The MPC9447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for
VCC=3.3V).
b. Inputs have pull-down or pull-up resistors affecting the input current.
c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 6. AC Characteristics (VCC = 3.3V ± 5%, TA = --40°C to +85°C)a
Symbol
5Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
0
fmax
Output Frequency
0
fP,REF
Reference Input Pulse Width
1.4
tr, tf
CCLK0, CCLK1 Input Rise/Fall Time
tPLH/HL Propagation Delay
CCLK0 or CCLK1 to any Q
1.3
tPLZ, HZ Output Disable Time
tPZL, ZH Output Enable Time
tS
Setup Time
CCLK0 or CCLK1 to CLK_STOPc
0.0
tH
Hold Time
CCLK0 or CCLK1 to CLK_STOPc
1.0
tsk(O)
Output-to-Output Skew
tsk(PP)
Device-to-Device Skew
tSK(P)
DCQ
Output Pulse Skewd
Output Duty Cycle
fQ<170 MHz
45
350
MHz
350
MHz
ns
1.0b
ns 0.8 to 2.0V
3.3
ns
11
ns
11
ns
ns
ns
150
ps
2.0
ns
300
ps
50
55
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns 0.55 to 2.4V
tJIT(CC) Cycle-to-cycle jitter
RMS (1 σ)
TBD
ps
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
b. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
c. Setup and hold times are referenced to the falling edge of the selected clock signal input.
d. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
TIMING SOLUTIONS
3
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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