MPC9443 Ver la hoja de datos (PDF) - Motorola => Freescale

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MPC9443

2.5V and 3.3V LVCMOS Clock Fanout Buffer

Motorola => Freescale 

MPC9443

Freescale Semiconductor, Inc.

Table 9: DC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 2.5V ± 5%, TA = –40 to +85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

VIH

Input High Voltage

1.7

VCC + 0.3

V

LVCMOS

VIL

Input Low Voltage

-0.3

0.7

V

LVCMOS

VPP

Peak-to-peak Input Voltage PCLK0,1

250

mV LVPECL

VCMRa Common Mode Range

PCLK0,1

1.1

IIN

Input Currentb

VOH

Output High Voltage

1.8

VOL

Output Low Voltage

ZOUT Output Impedance

VCC-0.7

V

LVPECL

200

µA VIN=GND or VIN=VCC

V

IOH= -15 mAc

0.6

V

IOL= 15 mAc

22

W

ICCQd Maximum Quiescent Supply Current

2.0

mA All VCC Pins

a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (DC) specification.

b. Input pull-up / pull-down resistors influence input current.

c. The MPC9443 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated

transmission line to a termination voltage of VTT. Alternatively, the device drives one 50Ω series terminated transmission lines at

VCC=2.5V.

d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.

Table 10: AC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 2.5 ± 5%, TA = –40 to +85°C)a

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

fMAX

Input Frequency

Maximum Output Frequency

0

÷1 output

0

÷2 output

0

350

MHz

350

MHz FSELx=0

175

MHz FSELx=1

VPP

Peak-to-peak input voltage

PCLK0,1

500

VCMRb

Common Mode Range

PCLK0,1

1.1

tP, REF

Reference Input Pulse Width

1.4

tr, tf

CCLK Input Rise/Fall Time

tPLH

tPHL

tPLH

tPHL

Propagation delay

PCLK0,1 to any Q

2.8

PCLK0,1 to any Q

2.7

CCLK to any Q

2.2

CCLK to any Q

2.1

tPLZ, HZ Output Disable Time

tPZL, LZ Output Enable Time

tS, tH

Setup, hold time (reference clock to CLK_STOP)

500

tsk(LH, HL)

Output-to-output Skewd

Within one bank

Any output, same output divider

Any output, any output divider

tsk(PP)

Device-to-device Skew (LH)e Using PCLK0,1

Using CCLK

Device-to-device Skew (LH, HL)f Using PCLK0,1

Using CCLK

tSK(p)

Output pulse skewg

Using PCLK0,1

Using CCLK

1000

VCC-0.7

1.0c

6.0

6.2

5.3

5.5

10

10

125

225

250

3.2

3.1

3.5

3.4

300

400

mV LVPECL

V

LVPECL

ns

ns 0.8 to 2.0V

ns

ns

ns

ns

ns

ns

ps

ps

ps

ps

ns

ns

ns

ns

ps DCREF = 50%

ps

DCQ

Output Duty Cycle fQ<140 MHz and using CCLK

45

50

55

%

fQ<250 MHz and using PCLK0,1

45

50

55

%

tr, tf

Output Rise/Fall Time

0.1

1.0

ns 0.6 to 1.8V

a. AC characteristics apply for parallel output termination of 50Ω to VTT.

b. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (AC) specification.

c. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input

pulse width, output duty cycle and maximum frequency specifications.

d. tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.

e. Device-to-device skew referenced to the rising output edge.

f. Device-to-device skew referenced to the rising output edge or referenced to the falling output edge.

g. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.

MOTOROLA

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