MPC9443 Ver la hoja de datos (PDF) - Motorola => Freescale

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componentes Descripción

Fabricante

MPC9443

2.5V and 3.3V LVCMOS Clock Fanout Buffer

Motorola => Freescale 

Freescale Semiconductor, Inc.

MPC9443

Table 1: Pin Configuration

Pin

CCLK

PCLK0, PCLK0

PCLK1, PCLK1

FSELA, FSELB, FSELC, FSELD

CCLK_SEL

PCLK_SEL

OE0, OE1

CLK_STOP

GND

VCCA, VCCB, VCCC, VCCD

VCC

QA0 to QA4

QB0 to QB2

QC0 to QC2

QD0 to QD4

I/O

Input

Input

Input

Input

Input

Input

Input

Input

Output

Output

Output

Output

Type

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

Supply

Supply

Supply

LVCMOS

LVCMOS

LVCMOS

LVCMOS

Function

LVCMOS clock inputs

LVPECL differential clock input

LVPECL differential clock input

Output bank divide select input

LVCMOS/LVPECL clock input select

PCLK0/PCLK1 clock input select

Output tristate control

Synchronous output enable/disable (clock stop) control

Negative voltage supply

Positive voltage supply output bank (VCC)

Positive voltage supply core (VCC)

Bank A outputs

Bank B outputs

Bank C outputs

Bank D outputs

Table 2: Supported Single and Dual Supply Configurations

Supply voltage

configuration

VCCa

VCCAb

VCCBc

VCCCd

VCCDe

3.3V supply

3.3V

3.3V

3.3V

3.3V

3.3V

Mixed mode supply

3.3V

3.3V or 2.5V

3.3V or 2.5V

3.3V or 2.5V

3.3V or 2.5V

2.5V supply

2.5V

2.5V

2.5V

2.5V

2.5V

a. VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels

b. VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels

c. VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels

d. VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels

e. VCCD is the positive power supply of the bank D outputs. VCCD voltage defines bank D output levels

GND

0V

0V

0V

Table 3: Function Table (Controls)

Control

CCLK_SEL

PCLK_SEL

FSELA

FSELB

FSELC

FSELD

CLK_STOP

Default

0

0

0

0

0

0

0

0

PCLK or PCLK1 active (LVPECL clock mode)

PCLK0 active, PCLK1 inactive

fQA0:4 = fREF

fQB0:2 = fREF

fQC0:2 = fREF

fQD0:4 = fREF

Normal operation

1

CCLK active (LVCMOS clock mode)

PCLK1 active, PCLK0 inactive

fQA0:4 = fREF ÷ 2

fQB0:2 = fREF ÷ 2

fQC0:2 = fREF ÷ 2

fQD0:4 = fREF ÷ 2

Outputs are synchronously disabled (stopped) in logic

low state

OE0, OE1

00

Asynchronous output enable control. See Table 4. OEN

TIMING SOLUTIONS

For More Informa3tion On This Product,

Go to: www.freescale.com

MOTOROLA

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