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MPC7457EC

RISC Microprocessor

Freescale Semiconductor 

Overview

1 Overview

The MPC7457 is the fourth implementation of the fourth generation (G4) microprocessors from Freescale.

The MPC7457 implements the full PowerPC 32-bit architecture and is targeted at networking and

computing systems applications. The MPC7457 consists of a processor core, a 512-Kbyte L2, and an

internal L3 tag and controller that support a glueless backside L3 cache through a dedicated

high-bandwidth interface. The MPC7447 is identical to the MPC7457 except that it does not support the

L3 cache interface.

Figure 1 shows a block diagram of the MPC7457. The core is a high-performance superscalar design

supporting a double-precision floating-point unit and a SIMD multimedia unit.

The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to

main memory and other system resources. The L3 interface supports 1, 2, or 4 Mbytes of external SRAM

for L3 cache and/or private memory data. For systems implementing 4 Mbytes of SRAM, a maximum of

2 Mbytes may be used as cache; the remaining 2 Mbytes must be private memory.

Note that the MPC7457 is a footprint-compatible, drop-in replacement in a MPC7455 application if the

core power supply is 1.3 V.

2 Features

This section summarizes features of the MPC7457 implementation of the PowerPC architecture.

Major features of the MPC7457 are as follows:

• High-performance, superscalar microprocessor

— As many as four instructions can be fetched from the instruction cache at a time.

— As many as three instructions can be dispatched to the issue queues at a time.

— As many as 12 instructions can be in the instruction queue (IQ).

— As many as 16 instructions can be at some stage of execution simultaneously.

— Single-cycle execution for most instructions

— One instruction per clock cycle throughput for most instructions

— Seven-stage pipeline control

• Eleven independent execution units and three register files

— Branch processing unit (BPU) features static and dynamic branch prediction

– 128-entry (32-set, four-way set associative) branch target instruction cache (BTIC), a cache

of branch instructions that have been encountered in branch/loop code sequences. If a target

instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can

be made available from the instruction cache. Typically, a fetch that hits the BTIC provides

the first four instructions in the target stream.

– 2048-entry branch history (BHT) with 2 bits per entry for 4 levels of prediction—not-taken,

strongly not-taken, taken, and strongly taken

– Up to three outstanding speculative branches

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8

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Freescale Semiconductor

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