MPC7457(2004) Ver la hoja de datos (PDF) - Freescale Semiconductor
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MPC7457 Datasheet PDF : 68 Pages
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Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441
Table 1. Microarchitecture Comparison (continued)
Microarchitectural Specs
MPC7457/MPC7447
MPC7455/MPC7445
MPC7450/MPC7451/
MPC7441
Parity on I cache
Parity on D cache
Number of D cache misses (load/store)
Data stream touch engines
Word
Byte
5/1
4 streams
Word
Byte
5/1
4 streams
Word
Byte
5/1
4 streams
On-Chip Cache Features
Cache level
Size/associativity
Access width
Number of 32-byte sectors/line
Parity
L2
L2
512-Kbyte/8-way
256-Kbyte/8-way
256 bits
256 bits
2
2
Byte
Byte
Off-Chip Cache Support 1
L2
256-Kbyte/8-way
256 bits
2
Byte
Cache level
Total SRAM space supported
L3
1 MB, 2MB, 4 MB 2
L3
1 MB, 2 MB
L3
1 MB, 2 MB
On-chip tag logical size (cache space)
1 MB, 2 MB
1 MB, 2 MB
1 MB, 2 MB
Associativity
8-way
8-way
8-way
Number of 32-byte sectors/line
2, 4
2, 4
2, 4
Off-Chip data SRAM support
MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2
Data path width
64
64
64
Direct mapped SRAM sizes
1 MB, 2 MB, 4 MB
1 MB, 2 MB
1 MB, 2 MB
Parity
Byte
Byte
Byte
Notes:
1. Not implemented on MPC7447, MPC7445, or MPC7441.
2. The MPC7457 supports up to 4 MB of SRAM, of which a maximum of 2 MB can be configured as cache memory; the
remaining 2 MB may be unused or configured as private memory.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
9
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