MPC7447 Ver la hoja de datos (PDF) - Freescale Semiconductor
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MPC7447 Datasheet PDF : 60 Pages
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System Design Information
9.2.4 Decoupling Recommendations
Due to the MPC7448 dynamic power management feature, large address and data buses, and high
operating frequencies, the MPC7448 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the MPC7448 system, and the MPC7448 itself requires a clean, tightly regulated
source of power. Therefore, it is recommended that the system designer use sufficient decoupling
capacitors, typically one capacitor for every VDD pin, and a similar amount for the OVDD pins, placed as
close as possible to the power pins of the MPC7448. It is also recommended that these decoupling
capacitors receive their power from separate VDD, OVDD, and GND power planes in the PCB, using short
traces to minimize inductance.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT)
capacitors should be used to minimize lead inductance. Orientations where connections are made along
the length of the part, such as 0204, are preferable but not mandatory. Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993) and contrary to previous recommendations for decoupling Freescale
microprocessors, multiple small capacitors of equal value are recommended over using multiple values of
capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time
necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors are 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
9.3 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unless otherwise noted, unused active low inputs should be tied to OVDD and unused active high
inputs should be connected to GND. All NC (no connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, and GND pins in the MPC7448.
For backward compatibility with the MPC7447, MPC7445, and MP7441, or for migrating a system
originally designed for one of these devices to the MPC7448, the new power and ground signals (formerly
NC, see Table 11) may be left unconnected if the core frequency is 1 GHz or less. Operation above 1 GHz
requires that these additional power and ground signals be connected, and it is strongly recommended that
all new designs include the additional connections. See also Section 7, “Pinout Listings,” for additional
information.
The MPC7448 provides VDD_SENSE, OVDD_SENSE, and GND_SENSE pins. These pins connect
directly to the power/ground planes in the device package and are intended to allow an external device to
measure the voltage present on the VDD, OVDD and GND planes in the device package. The most common
use for these signals is as a feedback signal to a power supply regulator to allow it to compensate for board
losses and supply the correct voltage at the device. (Note that all voltage parameters are specified at the
pins of the device.) If not used for this purpose, it is recommended that these signals be connected to test
points that can be used in the event that an accurate measurement of the voltage at the device is needed
during system debug. Otherwise, these signals should be connected to the appropriate power/ground
planes on the circuit board or left unconnected.
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor
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