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MPC7441

RISC Microprocessor Hardware Specifications

Freescale Semiconductor 

Electrical and Thermal Characteristics

5.2.3 IEEE Std. 1149.1 AC Timing Specifications

Table 10 provides the IEEE Std. 1149.1 (JTAG) AC timing specifications as defined in Figure 8 through

Figure 11.

Table 10. JTAG AC Timing Specifications (Independent of SYSCLK)1

At recommended operating conditions. See Table 4.

Parameter

Symbol

Min

Max

Unit

Notes

TCK frequency of operation

fTCLK

0

33.3

MHz

TCK cycle time

tTCLK

30

—

ns

TCK clock pulse width measured at 1.4 V

tJHJL

15

—

ns

TCK rise and fall times

tJR and tJF

—

2

ns

TRST assert time

tTRST

25

—

ns

2

Input setup times:

Boundary-scan data

TMS, TDI

tDVJH

4

tIVJH

0

ns

3

—

—

Input hold times:

Boundary-scan data

TMS, TDI

tDXJH

20

tIXJH

25

ns

3

—

—

Valid times:

Boundary-scan data

TDO

ns

4

tJLDV

4

20

tJLOV

4

25

Output hold times:

Boundary-scan data

TDO

ns

4

tJLDX

30

—

tJLOX

30

—

TCK to output high impedance:

Boundary-scan data

TDO

ns

4, 5

tJLDZ

3

19

tJLOZ

3

9

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 7).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Freescale Semiconductor

21

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